Test generation for ground bounce in internal logic circuitry

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 95-104

  Chang, Yi Shing ^a   Gupta, Sandeep K ^a   Breuer, Melvin A ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; SPURIOUS SIGNAL NOISE;

GROUND BOUNCE; INTERNAL LOGIC CIRCUITRY;

INTEGRATED CIRCUIT TESTING;

EID: 0032682923     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (12)