Power pin testing: making the test coverage complete

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 575-584

  de Jong, Frans ^a   Kup, Ben ^a   Schuttert, Rodger ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; ECONOMICS; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT TESTING; STANDARDS;

POWER PIN TESTING; STRUCTURAL TEST METHOD;

INTEGRATED CIRCUIT TESTING;

EID: 0034476563     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)