Contactless digital testing of IC pin leakage currents

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 204-210

  Sunter, Stephen ^a   McDonald, Charles ^a   Danialy, Givargis ^a  

^a LogicVision Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; EMBEDDED SYSTEMS; LEAKAGE CURRENTS; LOGIC PROGRAMMING;

DIGITAL TESTING; TEST PROGRAMS;

INTEGRATED CIRCUIT TESTING;

EID: 0035680694     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966635     Document Type: Article

References (8)

1. Low-cost testing of high-density logic components
2. Boundary-scan design principles for efficient LSSD ASIC testing
3. Delay testing of chip I/Os using LSSD boundary scan
4. Cost/benefit analysis of the P1149.4 mixed signal test bus
5. Early capture for boundary scan timing measurements