Tackling test trade-offs from design, manufacturing to market using economic modeling

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 1098-1107

  Volkerink, Erik H ^a,b   Khoche, Ajay ^a   Kamas, Linda A ^a   Rivoir, Jochen ^a   Kerkhoff, Hans G ^a,b  

^a AGILENT LABORATORIES   (United States)

^b UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

Economic modeling; Test cost optimization; Test cost trade offs; Test cost trends; Throughput analysis

Indexed keywords

CHIP SCALE PACKAGES; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE TESTING;

DIGITAL SEMICONDUCTOR PRODUCTION TESTS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0035684298     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966736     Document Type: Article

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