Delay test of chip I/Os using LSSD boundary scan

IEEE International Test Conference (TC)

Volumn , Issue , 1998, Pages 83-90

  Gillis, Pamela ^a   Woytowich, Francis ^a   McCauley, Kevin ^a   Baur, Ulrich ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SOFTWARE; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTERFACES (COMPUTER);

LEVEL-SENSITIVE SCAN DESIGN (LSSD) METHOD;

INTEGRATED CIRCUIT TESTING;

EID: 0032314393     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)