BIST-based diagnosis of FPGA interconnect

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 618-627

  Stroud, Charles ^a   Nall, Jeremy ^a   Lashinsky, Matthew ^a   Abramovici, Miron ^b  

^a University of North Carolina at Charlotte   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONFIGURABLE INTERCONNECT POINT; FAULTY WIRE SEGMENT; PROGRAMMABLE INTERCONNECT NETWORK; PROGRAMMABLE INTERCONNECT RESOURCE; PROGRAMMABLE SWITCH; TRANSMISSION GATE;

BUILT-IN SELF TEST; COMPUTER AIDED DESIGN; FAILURE ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; INTERCONNECTION NETWORKS; LOGIC DESIGN; LOGIC GATES; MULTIPLYING CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036443065     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2002.1041813     Document Type: Conference Paper

References (19)

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