Test methodology for interconnect structures of LUT-based FPGAs

Proceedings of the Asian Test Symposium

Volumn , Issue , 1996, Pages 68-74

  Michinishi, Hiroyuki ^a   Yokohira, Tokumi ^a   Okamoto, Takuji ^a   Inoue, Tomoo ^a   Fujiwara, Hideo ^a  

^a OKAYAMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGAS); PROGRAMMABLE POINTS;

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; ELECTRIC CONNECTORS; ELECTRIC FAULT CURRENTS; HEURISTIC METHODS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; SEMICONDUCTOR DEVICE STRUCTURES; TABLE LOOKUP;

LOGIC GATES;

EID: 0030411716     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. S. D. Brown, R. J. Francis, J. Rose and Z. G. Vranesic, "Field-programmable gate arrays," Kluwer Academic Publishers, 1992.
2. S. M. Trimberger, "Field-programmable gate array technology," Kluwer Academic Publishers, 1994.
3. The Programmable Logic Data Book, Xilinx Inc., 1994.
4. I. Pomcranz and S. M .Reddy, "Testability considerations in technology mapping," Proc. ATS '94, pp. 151-156, Nov. 1994.
5. H. Tsuboi, H.Nakada and T. Miyazaki, "Testing for circuits realized as FPGAs using register insertion method," Technical report of IEICE, FTS94-53, pp. 55-60, Oct. 1994.
6. T. Inoue, H. Fujiwara, H. Michinishi, T. Yokohira and T. Okamoto, "Universal Test Complexity of Field-Programmable Gate Arrays," Proc. ATS '95, pp. 259265, Nov. 1995.