Detectability conditions of full opens in the interconnections

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 17, Issue 2, 2001, Pages 85-95

  Zenteno, Antonio ^a   Champac, Victor H ^a   Figueras, Joan ^b  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Defect modeling; IDDQ testing; Logic testing; Opens

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES;

DRIVING GATE; INTERCONNECTION OPENS; LOGIC TESTING; SOFTWARE PACKAGE HSPICE;

INTEGRATED CIRCUIT TESTING;

EID: 0035299505     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1011179007753     Document Type: Article

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