Detectability conditions for interconnection open defects

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 305-311

  Champac, Victor H ^a   Zenteno, Antonio ^a  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DEFECTS; ELECTRIC CHARGE; GATES (TRANSISTOR); LOGIC GATES; MOSFET DEVICES;

ELECTRICAL MODELS; INTERCONNECTION OPEN DEFECTS;

BUILT-IN SELF TEST;

EID: 0033750909     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (23)