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Volumn 17, Issue 11, 1998, Pages 1200-1210

Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits

Author keywords

Integrated circuit testing; Logic circuit testing; Semiconductor defects

Indexed keywords

CIRCUIT OSCILLATIONS; CRYSTAL DEFECTS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; MICROPROCESSOR CHIPS;

EID: 0032206170     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.736192     Document Type: Article
Times cited : (9)

References (17)
  • 2
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    • V. H. Champac, A. Rubio, and J. Figueras, "Electrical model of th floating gate defect in CMOS IC's: Implications on IDDQ testing, IEEE Trans. Computer-Aided Design, vol. 13, pp. 359-369, Mar. 1994.
    • IEEE Trans. Computer-Aided Design
    • Champac, V.H.1    Rubio, A.2    Figueras, J.3
  • 3
    • 0027836999 scopus 로고    scopus 로고
    • "On accurate modeling and efficient simulatio of CMOS opens," in 1993, pp. 875-882.
    • C. Di and J. A. G. Jess, "On accurate modeling and efficient simulatio of CMOS opens," in Proc. Int. Test Conf., Oct. 1993, pp. 875-882.
    • Proc. Int. Test Conf., Oct.
    • Di, C.1    Jess, J.A.G.2
  • 6
    • 33747497317 scopus 로고    scopus 로고
    • "Residual charge on the faulty floating gate MOS transis- tors," in
    • S. Johnson, "Residual charge on the faulty floating gate MOS transis- tors," in Proc. Int. Test Conf., Oct. 1994.
    • Proc. Int. Test Conf., Oct. 1994.
    • Johnson, S.1
  • 8
    • 0029236385 scopus 로고    scopus 로고
    • "Accurate and efficien fault simulation of realistic CMOS network breaks," in 1995, pp. 345-351.
    • H. Konuk, F. J. Ferguson, and T. Larrabee, "Accurate and efficien fault simulation of realistic CMOS network breaks," in Proc. Desig Automation Conf., June 1995, pp. 345-351.
    • Proc. Desig Automation Conf., June
    • Konuk, H.1    Ferguson, F.J.2    Larrabee, T.3
  • 9
    • 0030393452 scopus 로고    scopus 로고
    • "Charge-based fault simulation for CMOS network breaks, vol. 15, pp. 1555-1567, Dec 1996.
    • "Charge-based fault simulation for CMOS network breaks, IEEE Trans. Computer-Aided Design, vol. 15, pp. 1555-1567, Dec 1996.
    • IEEE Trans. Computer-Aided Design
  • 15
    • 0026946275 scopus 로고    scopus 로고
    • "Electrical analysis and modeling o floating-gate fault," vol. 11, pp 1450-1458, Nov. 1992.
    • M. Renovell and G. Cambon, "Electrical analysis and modeling o floating-gate fault," IEEE Trans. Computer-Aided Design, vol. 11, pp 1450-1458, Nov. 1992.
    • IEEE Trans. Computer-Aided Design
    • Renovell, M.1    Cambon, G.2
  • 16


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.