On-line fault tolerance for FPGA interconnect with roving STARs

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 445-454

  Emmert, J ^a   Baumgart, S ^a   Kataria, P ^a   Taylor, A ^a   Stroud, C ^a   Abramovici, M ^a  

^a UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT TESTING; ONLINE SYSTEMS; RESOURCE ALLOCATION; ROUTERS;

FAULTY INTERCONNECT REUSE; PROGRAMMABLE INTERCONNECT RESOURCES;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 0035197986     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

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19. Built-in self-test of FPGA interconnect