Fault tolerant technique for FPGAs

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 6, 2000, Pages 591-606

  Emmert, John M ^a,c,d,e,f   Bhatia, Dinesh K ^b,g,h  

^a UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE   (United States)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

^c UNIVERSITY OF KENTUCKY   (United States)

^d AIR FORCE INSTITUTE OF TECHNOLOGY   (United States)

^e UNIVERSITY OF CINCINNATI   (United States)

^f University of North Carolina at Charlotte   (United States)

^g NATIONAL INSTITUTE OF TECHNOLOGY   (India)

^h The University of Texas at Dallas   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC DESIGN; MICROPROCESSOR CHIPS; SILICON;

INCREMENTAL PLACEMENT; INCREMENTAL RECONFIGURATION; INCREMENTAL ROUTING; MATCHING TECHNIQUE;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0034508112     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008365019152     Document Type: Article

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