Incremental routing in FPGAs

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1998, Pages 217-221

  Emmert, John M ^a   Bhatia, Dinesh ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; EMBEDDED SYSTEMS; LOGIC CIRCUITS;

INCREMENTALLY ROUTING CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0031636125     PISSN: 10630988     EISSN: None     Source Type: None    
DOI: 10.1109/ASIC.1998.722907     Document Type: Conference Paper

References (8)

1. D. Bhatia A. Chowdhary A Multi-Terminal Net Router for Field-Programmable Gate Arrays VLSI Design 4 1 10 1996
2. S. Brown J. Rose Z. G. Vranesic A Detailed Router for Field-Programmable Gate Arrays IEEE Transactions on Computer Aided Design 11 620 628 May 1992
3. S. D. Brown R. J. Fancis J. Rose Z. G. Vransic Field-Programmable Gate Arrays 1992 Kluwer Academic Publishers
4. J. M. Emmert D. K. Bhatia Lecture Notes in Computer Science 141 150 1997 Springer-Verlag Reconfiguring FPGA Mapped Designs with Applications to Fault Tolerance and Reconfigurable Computing
5. K. GajjalaPurna K. Simha P. Kannan D. Bhatia Lecture Notes in Computer Science 1998 Springer-Verlag REACT: Reactive Environment for Runtime Reconfiguration
6. F. Hanchek S. Dutt Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs Proceedings of the IEEE International Conference on VLSI Design 225 229 Proceedings of the IEEE International Conference on VLSI Design 1996-January
7. Xilinx CA, San Jose Xilinx Inc. http://www.xilinx.com
8. A. Mathur K. C. Chen C. L. Liu Reengineering of Timing Constrained Placements for Regular Architectures IEEE/ACM International Conference on Computer Aided Design 485 490 IEEE/ACM International Conference on Computer Aided Design 1995-November