Algorithms for efficient runtime fault recovery on diverse FPGA architectures

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1999, Pages 386-394

  Lach, John ^a   Mangione Smith, William H ^a   Potkonjak, Miodrag ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; FAULT TOLERANT COMPUTER SYSTEMS; FORMAL LOGIC; REDUNDANCY;

INTEGRATED CIRCUIT REDUNDANCY-BASED FAULT RECOVERY TECHNIQUES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0033357373     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)