Performance penalty for fault tolerance in roving STARs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1896, Issue , 2000, Pages 545-554

  Emmert, John M ^a   Stroud, Charles E ^a   Cheatham, Jason ^b   Taylor, Andrew M ^b   Kataria, Pankaj ^b   Abramovici, Miron ^c  

^a University of North Carolina at Charlotte   (United States)

^b UNIVERSITY OF KENTUCKY   (United States)

^c LUCENT TECHNOLOGIES   (United States)

Author keywords

Adaptive Computing System; Fault Tolerance; FPGA

Indexed keywords

BENCHMARKING; COMPUTATION THEORY; COMPUTER CIRCUITS; FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE ARCHITECTURES; STARS;

ADAPTIVE COMPUTING SYSTEMS; CRITICAL PATH DELAYS; FAULT-TOLERANT; INCREMENTAL CHANGES; ON-LINE TESTING; PERFORMANCE PENALTIES; SELF-TESTING; WORST-CASE PERFORMANCE;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 23044517771     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44614-1_59     Document Type: Conference Paper

References (15)

1. M. Abramovici, C. Stroud, S. Wijesuriya, C. Hamilton, and V. Verma. Using Roving STARs for On-Line and Diagnosis of FPGAs in Fault-Tolerant Applications. Proceedings of the 1999 International Test Conference, pages 973-982, October 1999.
2. S. Dutt, V. Shanmugavel, and S. Trimberger. Efficient Incremental Rerouting for Fault Reconfiguration in Field Programmable Gate Arrays. ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 1999.
3. J. M. Emmert and D. K. Bhatia. Reconfiguring FPGA Mapped Designs with Applications to Fault Tolerance and Reconfigurable Computing. In Lecture Notes in Computer Science, 7th International Workshop on Field Programmable Logic (FPL97), volume 1304, pages 141-150. Springer-Verlag, August/September 1997.
4. J. M. Emmert and D. K. Bhatia. Incremental Routing in FPGAs. In 11th Annual IEEE International ASIC Conference, pages I302-I305, September 1998.
5. J. M. Emmert, C. E. Stroud, B. Skaggs, and M. Abramovici. Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. In Eighth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, April 2000.
6. F. Hanchek and S. Dutt. Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. IEEE Transactions on Computers, 47:15-33, January 1998.
7. F. Hatori, T. Sakurai, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y. Kawahara, T. Hibi, Y. Sacki, H. Muraga, and K. Kanzaki. Introducing Redundancy in Field Programmable Gate Arrays. In Proceedings of the IEEE International Conference on Custom Integrated Circuits, pages 7.1.1-7.1.4, 1993.
8. Lucent Inc. http://www.micro.lucent.com/micro/fpga.
9. Xilinx Inc. http://www.xilinx.com.
10. J. L. Kelly and P. A. Ivey. A Novel Approach to Defect Tolerant Design for SRAM Based FPGAs. In ACMSecond InternationalWorkshop on Field-Programmable Gate Arrays, pages 1-11, Feburary 1994.
11. J. Lach, W. H. Mangione-Smith, and M. Potkonjak. Efficiently Supporting Fault Tolerance in FPGAs. In International Symposium on Field Programmable Gate Arrays, 1998.
12. V. Lakamraju and R. Tessier. Tolerating Operational Faults in Cluster-based FPGAs. In ACM International Symposium on Field-Programmable Gate Arrays, 2000.
13. K. Roy and S. Nag. On Routability for FPGAs under Faulty Conditions. IEEE Transactions on Computers, 44:1296-1305, November 1995.
14. G. Tempesti, D. Mange, and A. Stauffer. A Robust Multiplexer-Based FPGA Inspired By Biological Systems. In The Euromicro Journal, volume 43, September 1997.
15. M. Xu and F. J. Kurdahi. Accurate Prediction of Quality Metrics for Logic Level Designs Targeted Toward Lookup-Table-Based FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17:411-418, December 1999.