Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1304, Issue , 1997, Pages 141-150

  Emmert, John M ^a   Bhatia, Dinesh ^a  

^a University of Cincinnati   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0006845990     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63465-7_219     Document Type: Conference Paper

References (14)

1. S. D. Brown, R. J. hands, J. Rose, and Z. G. Vransic. Field-Programmable Gate Arrays. Kluwer Academic Publishers, 1992.
2. S. Durand and C. Piguet. FPGA with Selfrepair Capabilities. In ACM Second International Workshop on Field-Programmable Gate Arrays, pages 1-6, Feburary 1994.
3. S. Dutt and F. Hanchek. REMOD: A New Methodology for Designing Fault- Tolerant Arithmetic Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5:34-56, March 1997.
4. S. Even. Graph Algorithms. Computer Science Press, 1979.
5. F. Hanchek and S. Dutt. Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. In Proceedings of the IEEE International Conference on VLSI Design, pages 225-229, January 1996.
6. F. Hatori, T. Sakurai, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y. Kawahara, T. Hibi, Y. Sacki, H. Muraga, and K. Kanzaki. Introducing Redundancy in Field Programmable Gate Arrays. In Proceedings of the IEEE International Conference on Custom Integrated Circuits, pages 7.1.1-7.1.4, 1993.
7. N. J. Howard, A. M. Tyrrell, and N. M. Allinson. The Yield Enhancement of Field-Programmable Gate Arrays. IEEE Transactions on VLSI Systems, 2:115-123, March 1994.
8. Xilinx Inc. The Programmable Logic Data Book. Xilinx, 2100 Logic Drive, San Jose, CA 95124-3400, 1995.
9. J. L. Kelly and P. A. Ivey. A Novel Approach to Defect Tolerant Design for SRAM Based FPGAs. In ACM Second International Workshop on Field-Programmable Gate Arrays, pages 1-11, Feburary 1994.
10. K. Keutzer. Challenges in CAD for the One Million Gate FPGA. In ACM Fifth International Symposium on Field-Programmable Gate Arrays, pages 133-134, Feburary 1997.
11. F. T. Leighton and P. W. Shor. Tight Bounds for Minimax Grid Matching with Applications to Average Case Analysis of Algorithms. In Proceedings of the Symposium on Theory of Computing, pages 91-103, May 1986.
12. A. Mathur, K. C. Chen, and C. L. Liu. Re-engineering of Timing Constrained Placements for Regular Architectures. In IEEE/ACM International Conference on Computer Aided Design, pages 485-490, November 1995.
13. C. Papadimitriou and K. Steiglitz. Combinatorial Optimization. Prentice Hall Pubblishers, 1982.
14. J. Rose and D. Hill. Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond. In ACM Fifth International Symposium on Field- Programmable Gate Arrays, pages 129-132, Feburary 1997.