메뉴 건너뛰기




Volumn 1304, Issue , 1997, Pages 141-150

Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement

Author keywords

[No Author keywords available]

Indexed keywords


EID: 0006845990     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63465-7_219     Document Type: Conference Paper
Times cited : (29)

References (14)
  • 5
  • 8
    • 0003651029 scopus 로고
    • Xilinx, 2100 Logic Drive, San Jose, CA 95124-3400
    • Xilinx Inc. The Programmable Logic Data Book. Xilinx, 2100 Logic Drive, San Jose, CA 95124-3400, 1995.
    • (1995) The Programmable Logic Data Book
  • 11
    • 0005410063 scopus 로고
    • Tight Bounds for Minimax Grid Matching with Applications to Average Case Analysis of Algorithms
    • May
    • F. T. Leighton and P. W. Shor. Tight Bounds for Minimax Grid Matching with Applications to Average Case Analysis of Algorithms. In Proceedings of the Symposium on Theory of Computing, pages 91-103, May 1986.
    • (1986) Proceedings of the Symposium on Theory of Computing , pp. 91-103
    • Leighton, F.T.1    Shor, P.W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.