Modeling and extraction of interconnect capacitances fof multilayer VLSI circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 1, 1996, Pages 58-67

  Arora, Narain D ^a   Raol, Kartik V ^a   Schumann, Reinhard ^a   Richardson, Llanda M ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITANCE MEASUREMENT; COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; ELECTRIC WIRING; MATHEMATICAL MODELS; MULTILAYERS; THREE DIMENSIONAL; VLSI CIRCUITS;

CAPACITANCE EXTRACTION; CIRCUIT NETLIST; INTERCONNECT CAPACITANCES; LAYOUT GEOMETRY; THREE DIMENSIONAL SIMULATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029734640     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.486272     Document Type: Article

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