On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 487-490

  Qi, Xiaoning ^a   Wang, Gaofeng ^a   Yu, Zhiping ^a   Dutton, Robert W ^a   Young, Tak ^b   Chang, Norman ^c  

^a Stanford University   (United States)

^b SYNOPSYS INC   (United States)

^c HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC PROPERTIES; FREQUENCIES; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; INTERCONNECTION NETWORKS; MULTICHIP MODULES; SPURIOUS SIGNAL NOISE;

CRITICAL GLOBAL WIRE INDUCTIVE EFFECTS; GROUND INDUCTIVE NOISE; ON CHIP INDUCTABLE MODELLING; WHOLE CHIP EXTRACTION SCREENING PROCESS;

VLSI CIRCUITS;

EID: 0033712809     PISSN: 08865930     EISSN: None     Source Type: Journal    
DOI: 10.1109/CICC.2000.852714     Document Type: Article

References (6)

1. P. J. Restle High speed interconnects: a designers perspective ICCAD'98 Tutorial: Interconnect in high speed designs: problems, methodologies and tools ICCAD'98 Tutorial: Interconnect in high speed designs: problems, methodologies and tools 1998-Nov.
2. B. Kleveland X. Qi L. Madden R. Dutton S. Wong Line inductance extraction and modeling in a real chip with power grid IEDM'99 IEDM'99 1999-Dec.
3. Arcadia User Manual Synopsys Corp
4. M. Kamon M. J. Tsuk J. White FASTHENRY: a multipole accelerated 3D inductance extraction program IEEE Trans. Microwave Theory & Techniques 1750 1994
5. E. B. Rosa F. W. Grover Formulas and tables for the calculation of mutual and self-inductance 1916 Government Printing Office
6. L. He N. Chang S. Lin O. S. Nakagawa Efficient inductance modeling for on-chip interconnects IEEE CICC'99 457 IEEE CICC'99 1999