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Volumn , Issue , 2000, Pages 63-68

On-chip inductance modeling and analysis

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; CROSSTALK; ELECTRIC CONDUCTORS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC RESISTANCE; EQUIVALENT CIRCUITS;

EID: 0033685281     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2000.855278     Document Type: Article
Times cited : (65)

References (16)
  • 1
    • 0031246188 scopus 로고    scopus 로고
    • When are Transmission-Line Effects Important for On-Chip Interconnections?
    • A. Deutsch When are Transmission-Line Effects Important for On-Chip Interconnections? IEEE Transactions on MTT 1836 1847 Oct. 1997
    • (1997) IEEE Transactions on MTT , pp. 1836-1847
    • Deutsch, A.1
  • 2
    • 0031622874 scopus 로고    scopus 로고
    • Layout Based Frequency Depended Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis
    • B. Krauter Layout Based Frequency Depended Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis DAC 303 308 DAC 1998-June
    • (1998) , pp. 303-308
    • Krauter, B.1
  • 3
    • 0001613048 scopus 로고    scopus 로고
    • Mesh-Structured On-Chip Power/Ground: Design for Minimum Inductance and Characterization for Fast R, L Extraction
    • A. Sinha Mesh-Structured On-Chip Power/Ground: Design for Minimum Inductance and Characterization for Fast R, L Extraction CICC 461 464 CICC 1999-May
    • (1999) , pp. 461-464
    • Sinha, A.1
  • 4
    • 0031623454 scopus 로고    scopus 로고
    • Layout Techniques for Minimizing On-Chip Interconnect Self-Inductance
    • Y. Massoud Layout Techniques for Minimizing On-Chip Interconnect Self-Inductance DAC 566 571 DAC 1998-June
    • (1998) , pp. 566-571
    • Massoud, Y.1
  • 5
    • 0028498583 scopus 로고
    • FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program
    • M. Kamon FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program IEEE Transactions on MTT 1750 1758 Sept. 1994
    • (1994) IEEE Transactions on MTT , pp. 1750-1758
    • Kamon, M.1
  • 6
    • 0001032562 scopus 로고
    • Inductance Calculations in a Complex Integrated Circuit Environment
    • A. E. Ruehli Inductance Calculations in a Complex Integrated Circuit Environment IBM Journal of Research and Development 470 481 Sept. 1972
    • (1972) IBM Journal of Research and Development , pp. 470-481
    • Ruehli, A.E.1
  • 7
    • 0001169869 scopus 로고    scopus 로고
    • An Efficient Inductance Modeling for On-chip Interconnects
    • L. He An Efficient Inductance Modeling for On-chip Interconnects CICC 457 460 CICC 1999-May
    • (1999) , pp. 457-460
    • He, L.1
  • 8
    • 0030311976 scopus 로고    scopus 로고
    • Analysis and Design of Transmission-Line Structures by means of the Geometric Mean Distance
    • A. J. Sinclair Analysis and Design of Transmission-Line Structures by means of the Geometric Mean Distance IEEE Africon 1062 1065 IEEE Africon 1996-Sept.
    • (1996) , pp. 1062-1065
    • Sinclair, A.J.1
  • 9
    • 0003851263 scopus 로고
    • Inductance Calculations: Working Formulas and Tables
    • Dover Publications New York
    • F. W. Grover Inductance Calculations: Working Formulas and Tables 1946 Dover Publications New York
    • (1946)
    • Grover, F.W.1
  • 10
    • 0001038774 scopus 로고
    • Exact Inductance Equations for Rectangular Conductors with Applications to More Complicated Geometries
    • C. Hoer Exact Inductance Equations for Rectangular Conductors with Applications to More Complicated Geometries Journal of Research of the National Bureau of Standards 127 137 April-June 1965
    • (1965) Journal of Research of the National Bureau of Standards , pp. 127-137
    • Hoer, C.1
  • 11
    • 0029521458 scopus 로고
    • Generating Sparse Partial Inductance Matrices with guaranteed Stability
    • B. Krauter Generating Sparse Partial Inductance Matrices with guaranteed Stability ICCAD 45 52 ICCAD 1995-Nov.
    • (1995) , pp. 45-52
    • Krauter, B.1
  • 12
    • 0030645057 scopus 로고    scopus 로고
    • SPIE: Sparse Partial Inductance Extraction
    • Z. He SPIE: Sparse Partial Inductance Extraction DAC 137 140 DAC 1997-June
    • (1997) , pp. 137-140
    • He, Z.1
  • 13
    • 0002469282 scopus 로고    scopus 로고
    • Return-Limited Inductances: A Practical Approach to On-Chip Inductance Extraction
    • K. L. Shepard Return-Limited Inductances: A Practical Approach to On-Chip Inductance Extraction CICC 453 456 CICC 1999-May
    • (1999) , pp. 453-456
    • Shepard, K.L.1
  • 14
    • 0032629526 scopus 로고    scopus 로고
    • IC Analyses Including Extracted Inductance Models
    • M. W. Beattie IC Analyses Including Extracted Inductance Models DAC 915 920 DAC 1999-June
    • (1999) , pp. 915-920
    • Beattie, M.W.1
  • 15
    • 0032597772 scopus 로고    scopus 로고
    • Including Inductive Effects in Interconnect Timing Analysis
    • B. Krauter Including Inductive Effects in Interconnect Timing Analysis CICC 445 452 CICC 1999-May
    • (1999) , pp. 445-452
    • Krauter, B.1
  • 16
    • 0031378497 scopus 로고    scopus 로고
    • PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm
    • A. Odabasioglu PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm ICCAD 58 65 ICCAD 1997
    • (1997) , pp. 58-65
    • Odabasioglu, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.