-
1
-
-
0013067337
-
"The end of the road for Moore's law,"
-
6-11, 1999.
-
E. J. Lerner, "The end of the road for Moore's law," IBM J. Res. Develop., pp. 6-11, 1999.
-
IBM J. Res. Develop., Pp.
-
-
Lerner, E.J.1
-
2
-
-
0032679052
-
"MOS capacitance measurements for high-leakage thin dielectrics,"
-
vol. 46, pp. 1500-1501, July 1999.
-
K. J. Yang and C. Hu, "MOS capacitance measurements for high-leakage thin dielectrics," IEEE Trans. Electron Devices, vol. 46, pp. 1500-1501, July 1999.
-
IEEE Trans. Electron Devices
-
-
Yang, K.J.1
Hu, C.2
-
3
-
-
0032689170
-
"MOS C -V characterization of ultra-thin gate oxide thickness
-
(1.3-1.8 nm),"
-
C.-H. Choi et al, "MOS C -V characterization of ultra-thin gate oxide thickness (1.3-1.8 nm)," IEEE Electron Device Lett., vol. 20, pp. 292-294,June 1999.
-
IEEE Electron Device Lett., Vol. 20, Pp. 292-294,June 1999.
-
-
Choi, C.-H.1
-
4
-
-
0033169532
-
"Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-A gate oxide MOSFET's,"
-
vol. 46, pp. 1650-1655, Aug. 1999.
-
K. Ahmed étal., "Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-A gate oxide MOSFET's," IEEE Trans. Electron Devices, vol. 46, pp. 1650-1655, Aug. 1999.
-
IEEE Trans. Electron Devices
-
-
Ahmed, K.1
-
5
-
-
0033870951
-
"Limitations of Conductance to the measurement of the interface state density of MOS capacitors with tunneling gate dielectrics,"
-
vol. 47, pp. 601-608, Mar. 2000.
-
E. M. Vogel, W. K. Henson, C. A. Richter, and J. S. Suehle, "Limitations of Conductance to the measurement of the interface state density of MOS capacitors with tunneling gate dielectrics," IEEE Trans. Electron Devices, vol. 47, pp. 601-608, Mar. 2000.
-
IEEE Trans. Electron Devices
-
-
Vogel, E.M.1
Henson, W.K.2
Richter, C.A.3
Suehle, J.S.4
-
6
-
-
0032680955
-
"Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors,"
-
vol. 20, pp. 179-181, Apr. 1999.
-
W. K. Henson et al, "Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors," IEEE Electron Device Lett., vol. 20, pp. 179-181, Apr. 1999.
-
IEEE Electron Device Lett.
-
-
Henson, W.K.1
-
7
-
-
0030683249
-
"Modeling and characterization of n+ and p+ polysilicon-gated ultra thin oxides
-
(21-26 A)," 1997, pp. 149-150.
-
S. H. Eo et al, "Modeling and characterization of n+ and p+ polysilicon-gated ultra thin oxides (21-26 A)," in Proc. Symp. VLSI Technol., 1997, pp. 149-150.
-
In Proc. Symp. VLSI Technol.
-
-
Eo, S.H.1
-
9
-
-
0028396643
-
"A simple model for quantization effects in heavily-doped silicon MOSFET's at inversion conditions,"
-
vol. 37, p. 411, 1994.
-
M. J. van Dort, P. H. Woerlee, and A. J. Walker, "A simple model for quantization effects in heavily-doped silicon MOSFET's at inversion conditions," Solid-State Electron., vol. 37, p. 411, 1994.
-
Solid-State Electron.
-
-
Van Dort, M.J.1
Woerlee, P.H.2
Walker, A.J.3
-
10
-
-
0024751380
-
"Carrier transport near the Si/SiO2 interface of a MOSFET,"
-
vol. 32, p. 839, 1989.
-
W. Mansch, T. Vogelsang, R. Kircher, and M. Orlowski, "Carrier transport near the Si/SiO2 interface of a MOSFET," Solid-State Electron., vol. 32, p. 839, 1989.
-
Solid-State Electron.
-
-
Mansch, W.1
Vogelsang, T.2
Kircher, R.3
Orlowski, M.4
-
11
-
-
0030416118
-
"Accurate doping profile determination using TED/QM models extensible to sub-quarter micron nMOSFETs,"
-
1996, p. 811.
-
P. Vande Voorde et at., "Accurate doping profile determination using TED/QM models extensible to sub-quarter micron nMOSFETs," in IEDM Tech. Dig., 1996, p. 811.
-
In IEDM Tech. Dig.
-
-
Vande Voorde, P.1
-
12
-
-
84886448116
-
"Physical oxide thickness extraction and verification using quantum mechanical simulation,"
-
1997, pp. 869-872.
-
C. Bowen et al, "Physical oxide thickness extraction and verification using quantum mechanical simulation," in IEDM Tech. Dig., 1997, pp. 869-872.
-
In IEDM Tech. Dig.
-
-
Bowen, C.1
-
13
-
-
0001385164
-
"Mechanism of leakage current through the nano-scale SiO2 layer,"
-
vol. 75, p. 3530, 1994.
-
S. Nagano, M. Tsukiji, E. Hasegawa, and A. Ishitani, "Mechanism of leakage current through the nano-scale SiO2 layer," J. Appl. Phys., vol. 75, p. 3530, 1994.
-
J. Appl. Phys.
-
-
Nagano, S.1
Tsukiji, M.2
Hasegawa, E.3
Ishitani, A.4
-
14
-
-
33749901423
-
"Multi-dimensional quantum effect simulation using a density-gradient model and script-level programming techniques,"
-
1999, pp. 137-140.
-
C. S. Rafferty et al., "Multi-dimensional quantum effect simulation using a density-gradient model and script-level programming techniques," in Proc. Conf. Simulation Semiconductor Processes and Devices, 1999, pp. 137-140.
-
In Proc. Conf. Simulation Semiconductor Processes and Devices
-
-
Rafferty, C.S.1
-
15
-
-
0030212001
-
"1.5 nm direct-tunneling gate oxide Si MOSFET's,"
-
vol. 43, pp. 1233-1242, Aug. 1996.
-
H. S. Momose et al., "1.5 nm direct-tunneling gate oxide Si MOSFET's," IEEE Trans. Electron Devices, vol. 43, pp. 1233-1242, Aug. 1996.
-
IEEE Trans. Electron Devices
-
-
Momose, H.S.1
-
16
-
-
33749895164
-
"C -V and gate tunneling current characterization of ultra-thin gate oxide MOS (<.,. = 1.3-1.8 nm),"
-
1999, pp. 151-152.
-
C.-H. Choi etal., "C -V and gate tunneling current characterization of ultra-thin gate oxide MOS (<.,. = 1.3-1.8 nm)," in Proc. Symp. VLSI Technol., 1999, pp. 151-152.
-
In Proc. Symp. VLSI Technol.
-
-
Choi, C.-H.1
-
17
-
-
0032256946
-
"A study of flicker noise in N - AndP- MOSFET's with ultra-thin gate oxide in the direct-tunneling regime,"
-
1998, pp. 923-926.
-
H.S. Momose et al., "A study of flicker noise in N - andP- MOSFET's with ultra-thin gate oxide in the direct-tunneling regime," in IEDM Tech. Dig., 1998, pp. 923-926.
-
In IEDM Tech. Dig.
-
-
Momose, H.S.1
-
18
-
-
0032188244
-
"Ultrathin nitride/oxide (N/O) gate dielectrics for p+-polysilicon gated PMOSFET's prepared by a combined remote plasma enhanced CVD/thermal oxidation process,"
-
vol. 19, pp. 367-369, Oct. 1998.
-
Y. Wu and G. Eucovsky, "Ultrathin nitride/oxide (N/O) gate dielectrics for p+-polysilicon gated PMOSFET's prepared by a combined remote plasma enhanced CVD/thermal oxidation process," IEEE Electron Device Lett., vol. 19, pp. 367-369, Oct. 1998.
-
IEEE Electron Device Lett.
-
-
Wu, Y.1
Eucovsky, G.2
-
19
-
-
0033872334
-
"1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation process,"
-
vol. 21, pp. 116-118, Mar. 2000.
-
Y. Wu, Y.-M. Eee, and G. Eucovsky, "1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation process," IEEE Electron Device Lett., vol. 21, pp. 116-118, Mar. 2000.
-
IEEE Electron Device Lett.
-
-
Wu, Y.1
Eee, Y.-M.2
Eucovsky, G.3
-
20
-
-
0004146424
-
-
Englewood Cliffs, NJ: Prentice-Hall, 1998.
-
K. Kano, Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1998.
-
Semiconductor Devices.
-
-
Kano, K.1
-
23
-
-
0020180685
-
"General optimization and extraction of 1C device model parameters,"
-
vol. 30, pp. 1219-1228, Sept. 1983.
-
K. Doganis and D. E. Scharfetter, "General optimization and extraction of 1C device model parameters," IEEE Trans. Computer-Aided Design, vol. 30, pp. 1219-1228, Sept. 1983.
-
IEEE Trans. Computer-Aided Design
-
-
Doganis, K.1
Scharfetter, D.E.2
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