Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors

IEEE Electron Device Letters

Volumn 20, Issue 4, 1999, Pages 179-181

  Henson, W K ^a   Ahmed, K Z ^b   Vogel, E M ^c   Hauser, J R ^a   Wortman, J J ^a   Venables, R D ^a   Xu, M ^a   Venables, D ^a  

^a Campus Box 7908   (United States)

^b ADVANCED MICRO DEVICES   (United States)

^c NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; ELECTRIC RESISTANCE; LEAKAGE CURRENTS; THICKNESS MEASUREMENT; VOLTAGE MEASUREMENT;

TUNNEL OXIDES;

MOS CAPACITORS;

EID: 0032680955     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.753759     Document Type: Article

References (6)

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3. K. S. Krisch, J. D. Bude, and L. Manchanda, "Gate capacitance attenuation in MOS devices with thin gate oxides," IEEE Electron Device Lett., vol. 17, p. 512, Nov. 1996.
4. 2 films on nondegenerate Si," Solid State Electron., vol. 15, p. 221, 1972.
5. J. R. Hauser and K. Ahmed, "Characterization of ultrathin oxides using electrical C-V and I-V measurements," in Characterization and Metrology for ULSI Technology: 1998 Int. Conf., p. 235.
6. HP 4284 Operating Manual, Hewlett-Packard, Japan, p. 9-9, 1994.