Effects of thermal processes after silicidation on the performance of TiSi2/polysilicon gate device

IEEE Transactions on Electron Devices

Volumn 46, Issue 12, 1999, Pages 2353-2356

  Jang, Se Aug ^a   Kim, Tae Kyun ^a   Yeo, In Seok ^a   Kim, Hyeon Soo ^a   Lee, Sahng Kyoo ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

Mos devices; Polycide gate

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); SEMICONDUCTING FILMS; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE; TITANIUM COMPOUNDS;

SILICIDATION;

MOSFET DEVICES;

EID: 0033343313     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.808083     Document Type: Article

References (15)

1. T. Ohguro, S. Nakamura, M. Koike, T. Morimoto, A. Nishiyama, Y. Ushiku, T. Yoshitomi, M. Ono, M. Saito, and H. Iwai, "Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films," IEEE Trans. Electron Devices, vol. 41, pp. 2305-2317, Dec. 1994.
2. J. A. Kittl, Q. Z. Hong, M. Rodder, and T. Breedijk, "Novel one-step RTF Ti salicide process with low sheet resistance 0.06-//m gates and high drive current," in IEDM Tech. Dig., 1997, pp. 111-114.
3. C. Y. Ting, F. M. d'Heurle, S. S. lyer, and P. M. Fryer, "High temperature process limitation on TiSi2," J. Electrochem. Soc., vol. 133, no. 12, pp. 2621-2625, 1986.
4. J. F. Chen and L. J. Chen, "Morphological stability of TiSi2 on polycrystalline silicon," Thin Solid Films, vol. 293, pp. 34-39, 1997.
5. A. Kalnitsky, P. K. Hurley, and A. Lepert, "Dopants (P, As, and B) in the polycrystalline silicon/titanium suicide system: Redistribution and activation," J. Electrochem. Soc., vol. 144, no. 3, pp. 1090-1095, 1997.
6. C. Y. Lu, J. J. Sung, R. Liu, N. S. Tsai, R. Singh, S. J. Hillenius, and H. C. Kirsch, "Process limitation and device design trade-offs of self-aligned TiSi2 junction formation in submicrometer CMOS devices," IEEE Trans. Electron Devices, vol. 38, pp. 246-254, Feb. 1991.
7. C. L. Huang and N. D. Arora, "Measurements and modeling of MOSFET I-V characteristics with polysilicon depletion effect," IEEE Trans. Electron Devices, vol. 40, pp. 2330-2337, Dec. 1993.
8. N. D. Arora, R. Rios, and C. L. Huang, "Modeling the polysilicon depletion effect and its impact on submicrometer CMOS circuit performance," IEEE Trans. Electron Devices, vol. 42, pp. 935-943, May 1995.
9. B. Yu, D. H. Ju, W. C. Lee, N. Kepler, T. J. King, and C. Hu, "Gate engineering for deep-submicron CMOS transistors," IEEE Trans. Electron Devices, vol. 45, pp. 1253-1262, June 1998.
10. M. Orlowski, C. Mazure, and F. Lau, "Submicron short channel effects due to gate reoxidation induced lateral interstitial diffusion," in IEDM Tech. Dig., 1987, pp. 632-635.
11. D. K. Sadana, A. Acovic, G. Shahidi, H. Hanafi, A. C. Warren, D. Grutzmacher, F. Cardone, J. Sun, and B. Davari, "Enhanced short- channel effects in nMOSFET's due to boron redistribution induced by arsenic source and drain implant," in IEDM Tech. Dig., 1992, pp. 849-852.
12. P. K. Ko, T. Y. Chan, A. T. Wu, and C. Hu, "The effects of weak gate-to-drain (source) overlap on MOSFET characteristics," in IEDM Tech. Dig., 1986, pp. 292-295
13. T. Y. Chan, A. T. Wu, P. K. Ko, and C. Hu, "Effects of gate-to-drain/source overlap on MOSFET characteristics," IEEE Electron Device Lett., vol. EDL-8, pp. 326-328, July 1987.
14. P. K. Ko, S. Tarn, C. Hu, S. S. Wong, and C. G. Sodini, "Enhancement of hot-electron currents in graded-gate-oxide(GGO)-MOSFET's," in IEDM Tech. Dig., 1984, pp. 88-91.
15. H. Jiang and C. S. Petersson, "Thermal oxidation of transition metal suicides," Thin Solid Films, vol. 140, pp. 115-129, 1986.