Measurements and Modeling of MOSFET I-V Characteristics with Poly silicon Depletion Effect

IEEE Transactions on Electron Devices

Volumn 40, Issue 12, 1993, Pages 2330-2337

  Huang, Cheng Liang ^a   Arora, Narain D ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPOSITION EFFECTS; ELECTRIC CURRENT MEASUREMENT; GATES (TRANSISTOR); MATHEMATICAL MODELS; SEMICONDUCTING SILICON; SUBSTRATES; VOLTAGE MEASUREMENT;

DRAIN CURRENT DEGRADATION; OXIDE THICKNESS; PAO-SAH MODEL; POLYSILICON DEPLETION EFFECT; POLYSILICON GATE CONCENTRATION; SUBSTRATE IMPURITY CONCENTRATION;

MOSFET DEVICES;

EID: 0027872814     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.249483     Document Type: Article

References (31)

1. S. J. Hillenius and W. T. Lynch, “Gate material work function considerations for 0.5 micro CMOS,” in Proc. ICCD, p. 147, 1985.
2. G Yaron and D. Frohman-Bentchkowsky, “Capacitance voltage characterization of poly Si-Si0 2 -Si structure,” Solid-State Electron., vol. 23, p. 433, 1980.
3. R. A. Chapman, C. C. Wei, D. A. Bell, S. Aur, G. A. Brown, and R. A. Haken, “0.5 micron CMOS for high performance at 3.3 V,” in IEDM Tech. Dig., p. 52, 1988.
4. C. Y. Wong, J. Y.-C. Sun, Y. Taur, C. S. Oh, R. Angelucci, and B. Davari, “Doping of N + and P + polysilicon in a dual-gate CMOS process,” in IEDM Tech. Dig., p. 238, 1988.
5. C.-Y. Lu, J. M. Sung, H. C. Kirsch, S. J. Hillenius, T. E. Smith, and L. Manchanda, “Anomalous C-V characteristics of implanted poly MOS structure in n + /p + dual-gate CMOS technology,” IEEE Electron Dev. Lett., vol. 10, p. 192, 1989.
6. P. Habas and S. Selberherr, “On the effect of non-degenerate doping of polysilicon gate in the oxide MOS-devices—analytical modeling,” Solid-State Electron., vol. 33, p. 1539, 1990.
7. P. Habas and J. Faricelli, “Investigation of the physical modeling of the gate-depletion effect,” IEEE Trans. Electron Devices, vol. 39, p. 1496, 1992.
8. S.-W. Lee, C. Liang, C.-S. Pan, W. Lin, and J. B. Mark, “A study on the physical mechanism in the recovery of gate capacitance to C ox in implanted polysilicon MOS structure,” IEEE Electron Dev. Lett., vol. 13, p. 2, 1992.
9. B. Davari, W.-H. Chang, K. E. Petrillo, C. Y. Wong, D. Moy, Y. Taur, M. R. Wordeman, J. Y. C. Sun, C. C. H. Hsu, and M. R. Polcari, “A high-performance 0.25-µm CMOS technology: II-technology,” IEEE Trans. Electron Devices, vol. 39, p. 967, 1992.
10. C.-L. Huang, N. D. Arora, A. I. Nasr, and D. A. Bell, “Effect of polysilicon depletion on MOSFET I-V characteristics,” Electron. Lett., vol. 29, p. 1208, 1993.
11. E. H. Nicollian and J. R. Brews, MOS Physics and Technology. New York: Wiley, 1982, ch. 9 and 10.
12. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, ch. 7.
13. C.-L. Huang and G. Sh. Gildenblat, “MOS flat-band capacitance method at low temperatures,” IEEE Trans. Electron Devices, vol, ED-36, p. 1434, 1989.
14. R. C. Jaeger, F. H. Gaensslen, and S. E. Diehl, “An efficient numerical algorithm for simulation of MOS capacitance,” IEEE Trans. Computer-Aided Design, vol. CAD-2, p. 111 1983.
15. S. C. Jain and D. J. Roulston, “A simple expression for band gap narrowing (BGN) in heavily doped Si, Ge, GaAs and GeSi1-x strained layers,” Solid-State Electron., vol. 34, p. 453, 1991.
16. J. R. Pfiester, F. K. Baker, T. C. Mele, H.-H. Tseng, P. J. Tobin, J. D. Hayden, J. M. Miller, C. D. Gunderson, and L. C. Parrillo, “The effects of boron penetration on p + polysilicon gated pMOS devices,” IEEE Trans. Electron Devices, vol. 37, p. 1842, 1990.
17. K. Terada and H. Muta, “A new method to determine effective MOSFET channel length,” Jap. J. Appl. Phys., vol. 18, no. 5, p. 953, 1979.
18. N. Lifshitz, “Dependence of the work-function difference between the polysilicon gate and silicon substrate on the doping level in poly silicon,” IEEE Trans. Electron Devices, vol. ED-32, p. 617, 1985.
19. A. G. Sabnis and J. T. Clemens, “Characterization of the electron mobility in the inverted < 100 > Si surface,” IEDM Tech. Dig., p. 18, 1979.
20. J. Koomen, “Investigation of the MOST channel conductance in weak inversion,” Solid-State Electron., vol. 16, p. 801, 1973.
21. C. G. Sodini, T. W. Ekstedt, and J. L. Moll, “Charge accumulation and mobility in thin dielectric MOS transistors,” Solid-State Electron., vol. 25, p. 833, 1982.
22. C.-L. Huang and G. Sh. Gildenblat, “Correction factor in the split C-V method for mobility measurement,” Solid-State Electron., vol. 36, p. 611, 1993.
23. C.-L. Huang, J, Faricelli, and N. D. Arora. “A new technique for measuring MOSFET inversion layer mobility,” IEEE Trans. Electron Devices., vol. 40, p. 1134, 1993.
24. C.-L. Huang and G. Gildenblat, “Measurement and modeling of the n-channel MOSFET inversion layer mobility and device characteristics in the temperature range 60–300 K,” IEEE Trans. Electron Devices., vol. 37, p. 1285, 1990 and vol. 38, p. 680, 1991.
25. H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors,” Solid State Electron., vol. 9, p. 927, 1966.
26. C.-L. Huang and N. D. Arora, “Characterization and modeling of the n- and p-channel MOSFET's inversion-layer mobility in the temperature range 25 to 125°C,” in Solid-State Electron., to be published.
27. C.-L. Huang, “Characterization and modeling of MOS field-effect transistors in the 60–300 K temperature range,” Ph.D. Dissertation, The Pennsylvania State University, 1991.
28. R. C. Jaeger, and F. H. Gaensslen, “Simple analytical models for the temperature dependent threshold behavior of depletion-mode devices,” IEEE Trans. Electron Devices., vol. ED-26, p. 501, 1979.
29. X. Aymerich-Humet, F. Serra-Mestres, and J. Millan, “An analyli cal approximation for the Fermi-Dirac integral $ 3/2 (η) “Solid-State Electron., vol. 24, p. 981, 1981.
30. J. S. Blakemore, “Approximations for Fermi-Dirac integrals, especially the function 5” / 2 (Å) used to describe electron density in a semiconductor,” Solid-State Electron., vol. 25, p. 1067, 1982.
31. P. K. Ko, “Approaches to scaling,” in Advanced MOS Device Phys ics, N. G. Einspruch and G. Sh. Gildenblat, Eds. San Diego: Academic, 1988.