Effects of the Gate-to-Drain/Source Overlap on MOSFET Characteristics

IEEE Electron Device Letters

Volumn 8, Issue 7, 1987, Pages 326-328

  Chan, T Y ^a   Wu, A T ^a   Ko, P K ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTING SILICON - DOPING;

GATE-TO-DRAIN/SOURCE OVERLAP EFFECTS; IN-SITU DOPED POLYSILICON GATES; MOSFET CHARACTERISTICS;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0023383839     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1987.26647     Document Type: Article

References (8)

1. P. K. Ko et. al., “SiGMOS—A silicon gigabit/s NMOS technology,” in IEDM Tech. Dig., 1983, p. 751.
2. F.-C. Hsu and H. R. Grinolds, “Structure-enhanced MOSFHT degradation due to hot-electron injection,” IEEE Electron Device Lett., vol. EDL-5, p. 71, Mar. 1984.
3. J. Hui and J. Moll, “Submicrometer device design for hot-electron reliability and performance,” IEEE Electron Device Lett., vol. EDL-6, p. 350, July 1985.
4. F.-C. Hsu, J. Hui, and K. Y. Chiu, “Hot-electron degradation in submicron VLSI,” in IEDM Tech. Dig., 1985, p. 48.
5. T. Mizuno, Y. Matsumoto, S. Sawada, S. Shinozaki, and O. Ozawa, “A new degradation mechanism of current drivability and reliability of asymmetrical LDD MOSFET's,” in IEDM Tech. Dig., 1985, p. 250.
6. T. Y. Chan, A. T. Wu, P. K. Ko, and C. Hu, “Asymmetrical characteristics in LDD and minimum-overlap MOSFETs,” IEEE Electron Device Lett., vol. EDL-7, p. 16, Jan. 1986.
7. T. Y. Chan, A. T. Wu, P. K. Ko, and C. Hu, “A capacitance method to determine the gate-to-drain/source overlap length in MOSFET's,” IEEE Electron Device Lett., vol. EDL-8, no. 6, pp. 269–271, June 1987.
8. P. K. Ko, T. Y. Chan, A. T. Wu, and C. Hu, “The effects of weak gate-to-drain(source) overlap on MOSFET characteristics,” in IEDM Tech. Dig., 1986, p. 292.