-
1
-
-
0000901940
-
Fundamental limitations in microelectronics. I: MOS technology
-
B. Hoeneisen and C.A. Mead. "Fundamental limitations in microelectronics. I: MOS technology". Solid-State Electronics, 15:819-8296, 1972.
-
(1972)
Solid-State Electronics
, vol.15
, pp. 819-8296
-
-
Hoeneisen, B.1
Mead, C.A.2
-
2
-
-
0016116644
-
Design of ion-implanted MOSFETs with very small dimensions
-
April
-
R.H. Dennard. "Design of ion-implanted MOSFETs with very small dimensions". IEEE Journal of Solid-State Circuits, 9(2):256, April 1974.
-
(1974)
IEEE Journal of Solid-State Circuits
, vol.9
, Issue.2
, pp. 256
-
-
Dennard, R.H.1
-
3
-
-
0021406605
-
Generalized scaling theory and its application to a 1/4 micrometer MOSFET design
-
April
-
G. Baccarani, M.R. Wordeman, and R.H. Dennard. "Generalized scaling theory and its application to a 1/4 micrometer MOSFET design". IEEE Transactions on Electron Devices, 31(4):452-462, April 1984.
-
(1984)
IEEE Transactions on Electron Devices
, vol.31
, Issue.4
, pp. 452-462
-
-
Baccarani, G.1
Wordeman, M.R.2
Dennard, R.H.3
-
4
-
-
85056911965
-
Montecarlo simulation of a 30-nm dual gate MOSFET: How short can si go?
-
Washington
-
D.J. Frank, S.E. Laux, and M.V. Fischetti. "Montecarlo simulation of a 30-nm dual gate MOSFET: How short can si go?". IEDM Technical Digest, page 553, Washington, 1992.
-
(1992)
IEDM Technical Digest
, pp. 553
-
-
Frank, D.J.1
Laux, S.E.2
Fischetti, M.V.3
-
5
-
-
0028466732
-
Scaling of MOS technology to submicrometer feature sizes
-
C.A. Mead. "Scaling of MOS technology to submicrometer feature sizes". Analog Integrated Circuits and Signal Processing, 6(1):9-25, 1994.
-
(1994)
Analog Integrated Circuits and Signal Processing
, vol.6
, Issue.1
, pp. 9-25
-
-
Mead, C.A.1
-
6
-
-
0029292445
-
CMOS scaling for high performance and low power-the next ten years
-
April
-
B. Davari, R.H. Dennard, and G.G. Shahidi. "CMOS scaling for high performance and low power-the next ten years". Proceedings of the IEEE, 83(4):595-606, April 1995.
-
(1995)
Proceedings of the IEEE
, vol.83
, Issue.4
, pp. 595-606
-
-
Davari, B.1
Dennard, R.H.2
Shahidi, G.G.3
-
7
-
-
0026853681
-
Low power CMOS digital design
-
April
-
A.P. Chandrakasan, S. Sheng, and R. Brodersen. "Low power CMOS digital design". IEEE Journal of Solid-State Circuits, 27(4):473-483, April 1992.
-
(1992)
IEEE Journal of Solid-State Circuits
, vol.27
, Issue.4
, pp. 473-483
-
-
Chandrakasan, A.P.1
Sheng, S.2
Brodersen, R.3
-
9
-
-
0027594079
-
Future CMOS scaling and reliability
-
May
-
C. Hu. "Future CMOS scaling and reliability". Proceedings of the IEEE, 81(5):682-689, May 1993.
-
(1993)
Proceedings of the IEEE
, vol.81
, Issue.5
, pp. 682-689
-
-
Hu, C.1
-
10
-
-
0028388470
-
Hot-carrier-reliability design guidelines for CMOS logic circuits
-
March
-
K.N. Quader, E.R. Minami, W.-J. Huang, P.K. Ko, and C. Hu. "Hot-carrier-reliability design guidelines for CMOS logic circuits". IEEE Journal of Solid-State Circuits, 29(3):253-262, March 1994.
-
(1994)
IEEE Journal of Solid-State Circuits
, vol.29
, Issue.3
, pp. 253-262
-
-
Quader, K.N.1
Minami, E.R.2
Huang, W.-J.3
Ko, P.K.4
Hu, C.5
-
11
-
-
0002388796
-
DDQ: Origins, rediction, and applications in deep sub-um low power CMOS ICs
-
Washington
-
DDQ: Origins, rediction, and applications in deep sub-um low power CMOS ICs". Proceedings of the International Test Conference (ITC), pages 167-176, Washington, 1997.
-
(1997)
Proceedings of the International Test Conference (ITC)
, pp. 167-176
-
-
Keshavarzi, A.1
Roy, K.2
Hawkins, C.F.3
-
12
-
-
0029207481
-
Performance trends in high-end processors
-
January
-
G.A. Sai-Halasz. "Performance trends in high-end processors". Proceedings of the IEEE, 83(1):20-36, January 1995.
-
(1995)
Proceedings of the IEEE
, vol.83
, Issue.1
, pp. 20-36
-
-
Sai-Halasz, G.A.1
-
13
-
-
0030421285
-
Manufacturability of low power CMOS technology solutions
-
Monterey
-
A.J. Strojwas el al. "Manufacturability of low power CMOS technology solutions". Proceedings of the 1996 ISLPED, pages 225-232, Monterey, 1996.
-
(1996)
Proceedings of the 1996 ISLPED
, pp. 225-232
-
-
Strojwas, A.J.1
-
14
-
-
0028548950
-
Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's
-
November
-
T. Mizuno, J. Okamura, and A. Toriumi. "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's". IEEE Transactions on Electron Devices, 41(11):2216-2221, November 1994.
-
(1994)
IEEE Transactions on Electron Devices
, vol.41
, Issue.11
, pp. 2216-2221
-
-
Mizuno, T.1
Okamura, J.2
Toriumi, A.3
-
15
-
-
0029358972
-
Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation
-
August
-
S-W Sun and P.G. Tsui. "Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation". IEEE Journal of Solid-State Circuits, 30(8):947-949, August 1995.
-
(1995)
IEEE Journal of Solid-State Circuits
, vol.30
, Issue.8
, pp. 947-949
-
-
Sun, S.-W.1
Tsui, P.G.2
-
16
-
-
0031342511
-
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits
-
December
-
M. Eisele, J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf. "The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits". IEEE Transactions on VLSI Systems, 5(4):360-368, December 1997.
-
(1997)
IEEE Transactions on VLSI Systems
, vol.5
, Issue.4
, pp. 360-368
-
-
Eisele, M.1
Berthold, J.2
Schmitt-Landsiedel, D.3
Mahnkopf, R.4
-
17
-
-
0031270978
-
Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology
-
November
-
C.S. Murthy and M. Gall. "Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology". IEEE Transactions on Computer-Aided Design, 16(11):1383-1389, November 1997.
-
(1997)
IEEE Transactions on Computer-Aided Design
, vol.16
, Issue.11
, pp. 1383-1389
-
-
Murthy, C.S.1
Gall, M.2
-
18
-
-
0032206006
-
DDQ in submicron CMOS
-
November
-
DDQ in submicron CMOS". IEEE Transactions on Components, Packaging, and Manufacturing Technology Part B: Advanced Packaging, 21(4):352-359, November 1998.
-
(1998)
IEEE Transactions on Components, Packaging, and Manufacturing Technology Part B: Advanced Packaging
, vol.21
, Issue.4
, pp. 352-359
-
-
Figueras, J.1
Ferré, A.2
-
19
-
-
0000738845
-
Defect classes - An overdue paradigm for CMOS IC testing
-
C. Hawkins, J.M. Soden, A.W. Righter, and F.J. Ferguson. "Defect classes - An overdue paradigm for CMOS IC testing". Proceedings of the International Test Conference (ITC), pages 413-425, 1994.
-
(1994)
Proceedings of the International Test Conference (ITC)
, pp. 413-425
-
-
Hawkins, C.1
Soden, J.M.2
Righter, A.W.3
Ferguson, F.J.4
-
21
-
-
84976810569
-
Reaching agreement in the presence of faults
-
April
-
M. Pease, E. Shostak, and L. Lamport. "Reaching agreement in the presence of faults". Journal of the ACM, pages 228-234, April 1980.
-
(1980)
Journal of the ACM
, pp. 228-234
-
-
Pease, M.1
Shostak, E.2
Lamport, L.3
-
22
-
-
0031340072
-
So what is an optimal test mix? A discussion of the sernatech methods experiment
-
P.Nigh, W.Needham, K. Butler, P. Maxwell, R. Aitken, and W. Maly. "So what is an optimal test mix? A discussion of the sernatech methods experiment". Proceedings of the International Test Conference (ITC), pages 1037-1038, 1997.
-
(1997)
Proceedings of the International Test Conference (ITC)
, pp. 1037-1038
-
-
Nigh, P.1
Needham, W.2
Butler, K.3
Maxwell, P.4
Aitken, R.5
Maly, W.6
-
24
-
-
0031361502
-
DDQ testing of deep sub-micron technologies
-
Washington
-
DDQ Testing, pages 40-43, Washington, 1997.
-
(1997)
DDQ Testing
, pp. 40-43
-
-
Singh, A.D.1
-
28
-
-
0030645005
-
A novel probabilistic approach for ic diagnosis based on differential quiescent current signatures
-
C. Thibeault. "A novel probabilistic approach for ic diagnosis based on differential quiescent current signatures". Proceedings of 15th VLSI Test Symposium, pages 80-85, 1997.
-
(1997)
Proceedings of 15th VLSI Test Symposium
, pp. 80-85
-
-
Thibeault, C.1
-
30
-
-
0008494944
-
Tutorial on low power circuit design for multimedia LSI's
-
Paris
-
T. Sakurai. "Tutorial on low power circuit design for multimedia LSI's". European Design and Test Conference, Paris, 1997.
-
(1997)
European Design and Test Conference
-
-
Sakurai, T.1
-
33
-
-
0031274865
-
A 1-V programmable DSP for wireless communication
-
November
-
W. Lee, P.E. Landman, B. Barton, S. Abiko, H. Takahashi, H. Mizuno, S. Muramatsu, K. Tashiro, M. Fusumada, L. Pham, F. Boutaud, E. Ego, G. Gallo, H. Tran, C. Lemonds, A. Shih, M. Nandakumar, R. H. Eklund, and I.-C. Chen. "A 1-V programmable DSP for wireless communication". IEEE Journal of Solid-State Circuits, 32(11):1766-1776, November 1997.
-
(1997)
IEEE Journal of Solid-State Circuits
, vol.32
, Issue.11
, pp. 1766-1776
-
-
Lee, W.1
Landman, P.E.2
Barton, B.3
Abiko, S.4
Takahashi, H.5
Mizuno, H.6
Muramatsu, S.7
Tashiro, K.8
Fusumada, M.9
Pham, L.10
Boutaud, F.11
Ego, E.12
Gallo, G.13
Tran, H.14
Lemonds, C.15
Shih, A.16
Nandakumar, M.17
Eklund, R.H.18
Chen, I.-C.19
-
34
-
-
0031122158
-
CMOS scaling into the nanometer regime
-
April
-
Y. Taur, D.A. Buchanan, W. Chen, D.J. Frank, K.E. Ismail, S.-H. Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind, and H.-S. Wong. "CMOS scaling into the nanometer regime". Proceedings of the IEEE, 85(4):486-504, April 1997.
-
(1997)
Proceedings of the IEEE
, vol.85
, Issue.4
, pp. 486-504
-
-
Taur, Y.1
Buchanan, D.A.2
Chen, W.3
Frank, D.J.4
Ismail, K.E.5
Lo, S.-H.6
Sai-Halasz, G.A.7
Viswanathan, R.G.8
Wann, H.-J.C.9
Wind, S.J.10
Wong, H.-S.11
-
35
-
-
0031164495
-
A low-resistance self-aligned T-shaped gate for high-performance sub0.1-μm CMOS
-
June
-
D. Hisamoto, K. Umeda, Y. Nakamura, and S. Kimura. "A low-resistance self-aligned T-shaped gate for high-performance sub0.1-μm CMOS". IEEE Transactions on Electron Devices, 44(6):951-956, June 1997.
-
(1997)
IEEE Transactions on Electron Devices
, vol.44
, Issue.6
, pp. 951-956
-
-
Hisamoto, D.1
Umeda, K.2
Nakamura, Y.3
Kimura, S.4
-
40
-
-
0025460949
-
Quiescent current sensor circuits in digital VLSI CMOS testing
-
July
-
A. Rubio, J. Figueras, and J. Segura. "Quiescent current sensor circuits in digital VLSI CMOS testing". Electronics Letters, 26:1204-1206, July 1990.
-
(1990)
Electronics Letters
, vol.26
, pp. 1204-1206
-
-
Rubio, A.1
Figueras, J.2
Segura, J.3
-
47
-
-
0001149184
-
Design for testability of embedded integrated operational amplifiers
-
April
-
Karim Arabi and Bozena Kaminska. "Design for testability of embedded integrated operational amplifiers". IEEE Journal of Solid-State Circuits, 33(4):573-581, April, 1998.
-
(1998)
IEEE Journal of Solid-State Circuits
, vol.33
, Issue.4
, pp. 573-581
-
-
Arabi, K.1
Kaminska, B.2
-
49
-
-
0031343438
-
Analog and mixed-signal benchmark circuits - First release
-
Washington, D.C., USA. November 1-6
-
B. Kaminska, K. Arabi, I. Bell, P. Goteti, J.L. Huertas, B. Kim, A. Rueda, and M. Soma. "Analog and mixed-signal benchmark circuits - First release". Proceedings of the IEEE International Test Conference, Washington, D.C., USA. November 1-6, 1997.
-
(1997)
Proceedings of the IEEE International Test Conference
-
-
Kaminska, B.1
Arabi, K.2
Bell, I.3
Goteti, P.4
Huertas, J.L.5
Kim, B.6
Rueda, A.7
Soma, M.8
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