Hierarchical test generation and design for testability methods for aspp's and ASIP's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 2-3, 1999, Pages 357-370

  Ghosh, Indradeep ^a,b   Raghunathan, Anand ^a,b   Jha, Niraj K ^a,b  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

Application specific instruction processors (as ip's); Application specific programmable processors (aspp's); Design for testability; Hierarchical testing; Symbolic testing

Indexed keywords

APPLICATION SPECIFIC INSTRUCTION PROCESSORS (ASIP); APPLICATION SPECIFIC PROGRAMMABLE PROCESSORS (ASPP); HIERARCHICAL TEST GENERATION TECHNIQUES; REGISTER TRANSFER LEVEL (RTL);

DATA FLOW ANALYSIS; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT TESTING; ROM;

MICROPROCESSOR CHIPS;

EID: 0033089770     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.748165     Document Type: Article

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