Hierarchical test generation under intensive global functional constraints

Proceedings - Design Automation Conference

Volumn , Issue , 1992, Pages 261-266

  Lee, Jaushin ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; LOGIC GATES; VLSI CIRCUITS;

MODULE TEST COMPUTATION;

INTEGRATED CIRCUIT TESTING;

EID: 0026971706     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)