Test Generation for Data-Path Logic: The F-Path Method

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 2, 1988, Pages 421-427

  Freeman, Smith ^a  

^a SARNOFF CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI - TESTING;

DATA-PATH LOGIC; F-PATH (FAULT PATH) METHOD; TEST GENERATION;

LOGIC CIRCUITS;

EID: 0023997329     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.1002     Document Type: Article

References (5)

1. M. S. Abadir and M. A. Breuer, “A knowledge-based system for designing testable VLSI chips,” IEEE Design Test, pp. 56–68, Aug. 1985.
2. M. S. Abadir and M. A. Breuer, “Test schedules for VLSI circuits having built-in test hardware,” IEEE Trans. Comput., vol. C-35, pp. 361–367, Apr. 1985.
3. L. R. Tate, “Sparse canonical signed digit FIR filter,” in Proc. IEEE 1987 CICC ‘Portland, OR’, May 1987, pp. 215–218.
4. T. H. Bui, “A highspeed LMS adaptive filter,” in Proc. IEEE 1987 CICC ‘Portland, OR’, May 1987, pp. 227–229.
5. S. Freeman, “The F-path method of test generation for datapath logic,” in Proc. IEEE 1987 CICC ‘Portland, OR’, May 1987, pp. 72–77.