Dynamic test sequence compaction for sequential circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 170-173

  Raghunathan, Anand ^a   Chakradhar, Srimat T ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ERROR DETECTION; FORMAL LOGIC; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS; MATHEMATICAL MODELS; RANDOM PROCESSES; VECTORS;

ANCHOR VECTOR; DYNAMIC TEST SEQUENCE COMPACTION; FAULT EFFECTS; FULL SCAN DESIGN CIRCUITS; PRIMARY TEST GENERATION; PRIMARY TEST SEQUENCE; SECONDARY TARGET FAULTS; SECONDARY TEST GENERATION; SLIDING ANCHOR FRAME; TEST GENERATOR;

SEQUENTIAL CIRCUITS;

EID: 0029697591     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)