A BIST scheme for RTL controller-data paths based on symbolic testability analysis

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 554-559

  Ghosh, Indradeep ^a   Jha, Niraj K ^a   Bhawmik, Sudipta ^b  

^a Princeton University   (United States)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROLLERS; ELECTRIC NETWORK ANALYSIS; COMPUTER ARCHITECTURE; CONTROL SYSTEM SYNTHESIS; CONTROLLABILITY; OBSERVABILITY;

BIST ARCHITECTURES; CONTROLLABILITY AND OBSERVABILITIES; PROPAGATION PATHS; PSEUDORANDOM PATTERN GENERATORS; REGISTER TRANSFER LEVEL; SIGNATURE ANALYZERS; TEST ENVIRONMENT; TESTABILITY ANALYSIS;

BUILT-IN SELF TEST; DATA FLOW ANALYSIS;

BUILT-IN SELF-TEST (BIST) RESOURCES; REGISTER-TRANSFER LEVELS;

EID: 0031619491     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277192     Document Type: Conference Paper

References (16)

1. J. M. Rabaey, Digital Integrated Circuits, A Design Perspective, Prentice Hall, Inc., New Jersey, 1996.
2. D. A. Priore, "Inductance on Silicon for Sub-Micron CMOS VLSI, " Proceedings of the IEEE Symposium on VLSI Circuits, pp. 17-18, May 1993.
3. D. B. Jarvis, "The Effects of Interconnections on HighSpeed Logic Circuits, " IEEE Transactions on Electronic Computers, Vol. EC-10, No. 4, pp. 476 - 487, October 1963.
4. M. P. May, A. Taflove, and J. Baron, "FD-TD Modeling of Digital Signal Propagation in 3-D Circuits with Passive and Active Loads, " IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-42, No. 8, pp. 1514 - 1523, August 1994.
5. T. Sakurai, "Approximation of Wiring Delay in MOSFET LSI, " IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 4, pp. 418 - 426, August 1983.
6. G. Y. Yacoub, H. Pham, M. Ma, and E. G. Friedman, "A System for Critical Path Analysis Based on Back Annotation and Distributed Interconnect Impedance Models, " Microelectronic Journal, Vol. 18, No. 3, pp. 21 - 30, June 1988.
7. J. Torres, "Advanced Copper Interconnections for Silicon CMOS Technologies, " Applied Surface Science, Vol. 91, No. 1, pp. 112 - 123, October 1995.
8. K. K. Likharev and V. K. Semenov, "RSFQ Logic/Memory Family: A New Josephson-Junction Technology for Sub-Terahertz-Clock Frequency Digital System, " IEEE Transactions on Applied Superconductivity, Vol. AS-1, No. 1, pp. 3 - 28, March 1991.
9. T. Sakurai and A. R. Newton "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas, " IEEE Journal of Solid-State Circuits, Vol. SC-25, No. 2, pp. 584 - 593, April 1990.
10. AS/X User's Guide, IBM Corporation, New York, 1996.
11. L. N. Dworsky, Modem Transmission Line Theory and Applications, John Wiley & Sons, Inc., New York, 1979.
12. Y. Eo and W. R. Eisenstadt, "High-Speed VLSI Interconnect Modeling Based on S-Parameter Measurement, " IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-16, No. 5, pp. 555 - 562, August 1993.
13. A. Deutsch, et al., "High-Speed Signal Propagation on lossy transmission lines, " IBM Journal of Research and Development, Vol. 34, No. 4, pp. 601 - 615, July 1990.
14. A. Deutsch, et al., "Modeling and Characterization of Long Interconnections for High-Performance Microprocessors, " IBM Journal of Research and Development, Vol. 39, No. 5, pp. 547 - 667, September 1995.
15. A. Deutsch, et al., "When are transmission-line effects important for on-chip interconnections?, " IEEE Transactions on Microwave Theory and Techniques, Vol. 45, No. 10, pp. 1836 - 1846, October 1997.
16. M. Shoji, High-Speed Digital Circuits, Addison Wesley, Massachusetts, 1996.