Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1994, Pages 91-96

  Bhatia, Sandeep ^a   Jha, Niraj K ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTRIC NETWORK SYNTHESIS; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; POLES AND ZEROS;

BEHAVIORAL SYNTHESIS; CONDITIONAL BRANCHES; CONTROLLER/DATA PATH CIRCUITS; HIERARCHICAL TESTABILITY;

DIGITAL CIRCUITS;

EID: 0028747189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)