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Volumn 45, Issue 5, 1998, Pages 1099-1104

Thin suicide development for fully-depleted SOI CMOS technology

Author keywords

CMOSFET's; Contacts; Fully depleted; Silicon on insulator technology; Suicide

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTIVITY OF SOLIDS; ELECTRIC RESISTANCE; SEMICONDUCTING SILICON COMPOUNDS; TRANSMISSION LINE THEORY; ULTRATHIN FILMS;

EID: 0032071043     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.669543     Document Type: Article
Times cited : (19)

References (16)
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  • 8
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    • P. P. Apte, A. Paranjpe, and G. Pollack, "Use of a TIN cap to attain low sheet resistance for scaled TiSi2 on sub-half-micrometer polysilicon lines," IEEE Electron Device Lett., 17, pp. 506-508, Nov. 1996.
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  • 10
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    • "A novel suicide technology for thin film SOI MOSFET's using Ge preamorphization," in
    • T. C. Hsiao, P. Liu, and J. C. S. Woo, "A novel suicide technology for thin film SOI MOSFET's using Ge preamorphization," in IEEE SOI Conf., 1996, pp. 126-127.
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    • Hsiao, T.C.1    Liu, P.2    Woo, J.C.S.3
  • 12
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.