Gate Electrode RC Delay Effects in VLSI’s

IEEE Transactions on Electron Devices

Volumn 32, Issue 2, 1985, Pages 370-374

  Sakurai, Takayasu ^a   Iizuka, Tetsuya ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84945716084     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1985.21951     Document Type: Article

References (9)

1. T. Sakurai and T. Iizuka, “Double word line and bit line structure for VLSI RAM’s,” in Proc. 15th Conf. Solid State Devices and Materials, pp. 269–272, 1983.
2. K. Anami, M. Yoshimoto, H. Shinohara, O. Tomisawa, and T. Nakano, “Analysis of parasitic resistance effects in MOS LSI,” IECE of Japan, vol. J66-C, no. 9, pp. 646–652, Sept. 1983.
3. H. C. Lin, Y. F. Arzoumanian, J.L. Halsor, M. N. Giuliano, and H. F. Benz, “Effect of silicon-gate resistance on the frequency response of MOS transistors,” IEEE Trans, Electron Devices, vol. ED-22, pp. 255–264, May 1975.
4. T. Sakurai, J. Matsunaga, M. Isobe, T. Ohtani, K. Sawada, A. Aono, H. Nozawa, T. Iizuka, and S. Kohyama, “A low power 46ns 256Kbit CMOS static RAM with dynamic double word line,” IEEE J. Solid-State Circuits, vol. SC-19, no. 5, Oct. 1984.
5. T. Sakurai, “Approximation of wiring delay in MOSFET LSI,” IEEE J. Solid-State Circuits, vol. SC-18, no. 4, pp. 418–426, Aug. 1983.
6. T. Sakurai, T. Furuyama, and T. Iizuka, “Methods for analyzing a word line delay and their applications,” The Community of Solid State Device of IECE of Japan, vol. SSD82, p. 15, Oct. 1982.
7. C. T. Sah, “Characteristics of metal-oxide-semiconductor transistors,” IEEE Trans. Electron Devices, vol. ED-11, pp. 324–345, July 1964.
8. L. W. Nagel, “A computer program to simulate semiconductor circuits,” U. C. Berkeley Memo ERL-M520, May 1975.
9. T. Sakurai and K. Tamaru, “Simple formulas for two- and three-dimensional capacitances,” IEEE Trans. Electron Devices, vol. ED-30, pp. 183–185, Feb. 1983.