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Volumn 17, Issue 11, 1996, Pages 506-508

Use of a TiN cap to attain low sheet resistance for scaled TiSi2 on sub-half-micrometer polysilicon lines

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CONDUCTIVITY; ELECTRIC RESISTANCE; PHASE TRANSITIONS; SEMICONDUCTING FILMS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DOPING; TITANIUM NITRIDE;

EID: 0030291120     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.541763     Document Type: Article
Times cited : (10)

References (8)
  • 2
    • 84947303539 scopus 로고
    • A new three-dimensional MOSFET gate-induced drain leakage effect in narrow deep submicron devices
    • S. Geissler, B. Porth, J. Lasky, J. Johnson, and S. Voldman, "A new three-dimensional MOSFET gate-induced drain leakage effect in narrow deep submicron devices," in IEDM Tech. Dig., 1991, p. 839.
    • (1991) IEDM Tech. Dig. , pp. 839
    • Geissler, S.1    Porth, B.2    Lasky, J.3    Johnson, J.4    Voldman, S.5
  • 3
    • 0029227582 scopus 로고
    • W/Ti self-aligned silicidation process for 0.25 μm CMOS
    • K. Inoue, K. Fujii, K. Mikagi, and T. Kikkawa, "W/Ti self-aligned silicidation process for 0.25 μm CMOS," NEC Res. Develop., vol. 36, no. 1, p. 114, 1995.
    • (1995) NEC Res. Develop. , vol.36 , Issue.1 , pp. 114
    • Inoue, K.1    Fujii, K.2    Mikagi, K.3    Kikkawa, T.4
  • 4
    • 0029332351 scopus 로고
    • Silicides and local interconnections for high performance VLSI applications
    • R. W. Mann, L. A. Clevenger, P. D. Agnello, and F. R. White, "Silicides and local interconnections for high performance VLSI applications," IBM J. Res. Develop., vol. 39, no. 4, p. 403, 1995.
    • (1995) IBM J. Res. Develop. , vol.39 , Issue.4 , pp. 403
    • Mann, R.W.1    Clevenger, L.A.2    Agnello, P.D.3    White, F.R.4
  • 7
    • 0027889412 scopus 로고
    • 21 psec switching 0.1 μm-CMOS at room temperature using high performance co-salicide process
    • T. Yamazaki, K. Goto, T. Fukano, Y. Nara, T. Sugii, T. Ito, "21 psec switching 0.1 μm-CMOS at room temperature using high performance co-salicide process," in IEDM Tech. Dig., 1993, p. 906.
    • (1993) IEDM Tech. Dig. , pp. 906
    • Yamazaki, T.1    Goto, K.2    Fukano, T.3    Nara, Y.4    Sugii, T.5    Ito, T.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.