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Volumn 8, Issue 1, 1995, Pages 83-114

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

Author keywords

device modeling; low current; low voltage; MOS transistor

Indexed keywords

CAPACITANCE; ELECTRIC CHARGE; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; FUNCTIONS; GATES (TRANSISTOR); INTERPOLATION; SEMICONDUCTOR DEVICE MODELS; SPURIOUS SIGNAL NOISE; THERMAL NOISE; TRANSCONDUCTANCE;

EID: 0029342165     PISSN: 09251030     EISSN: 15731979     Source Type: Journal    
DOI: 10.1007/BF01239381     Document Type: Article
Times cited : (951)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.