The path-status graph with application to delay fault simulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 4, 1998, Pages 324-332

  Gharaybeh, Marwan A ^a   Bushnell, Michael L ^b,c,d   Agrawal, Vishwani D ^b,c,d  

^a RUTGERS UNIVERSITY   (United States)

^b SYNOPSYS INC   (United States)

^c RUTGERS UNIVERSITY   (United States)

^d LUCENT TECHNOLOGIES   (United States)

Author keywords

Delay testing; Fault simulation; Path delay fault

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DATA STRUCTURES; GRAPH THEORY;

PATH DELAY FAULT (PDF) SIMULATORS; PATH STATUS GRAPH (PSG);

COMBINATORIAL CIRCUITS;

EID: 0032044561     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.703822     Document Type: Article

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