Circuit Structure Relations to Redundancy and Delay

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 7, 1994, Pages 875-883

  Saldanha, Alexander ^a   Brayton, Robert K ^b   Sangiovanni Vincentelli, Alberto L ^b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CIRCUIT THEORY; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; EQUIVALENT CIRCUITS; FAILURE ANALYSIS; ITERATIVE METHODS; LOGIC GATES; PERFORMANCE; REDUNDANCY; RELIABILITY;

CIRCUIT STRUCTURE; ITERATIVE LOOP; LOGIC SYNTHESIS; REDUNDANT STUCK FAULTS; TESTABILITY; TIMING ANALYSIS;

COMBINATORIAL CIRCUITS;

EID: 0028460484     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.293944     Document Type: Article

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