Improving accuracy in path delay fault coverage estimation

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 422-425

  Heragu, Keerthi ^a   Patel, Janak H ^a   Agrawal, Vishwani D ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ERROR DETECTION; ESTIMATION; FAILURE ANALYSIS; GRAPH THEORY; VECTORS;

FAULT SIMULATOR; PATH DELAY FAULT; SIMULATED VECTOR PAIR;

VLSI CIRCUITS;

EID: 0029724650     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)