An efficient method for computing exact path delay fault coverage

Proceedings of the 1995 European Conference on Design and Test, EDTC 1995

Volumn , Issue , 1995, Pages 516-520

  Kapoor, Bhanu ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STRUCTURES; ELECTRIC FAULT CURRENTS; TREES (MATHEMATICS);

ALGORITHMS AND DATA STRUCTURES; BENCHMARK CIRCUIT; EFFICIENT COMPUTATION; KEEP TRACK OF; PATH DELAY FAULT; ROBUST SIMULATIONS; TREE DATA STRUCTURES;

COMPUTATIONAL EFFICIENCY;

EID: 0003384201     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/edtc.1995.470352     Document Type: Conference Paper

References (16)

1. A. V. Aho, J. E. Hopcroft, and J. D. Ullman. Data Structures and Algorithms. Addison-Wesley Publishing Company, Reading, MA, 1983.
2. Z. Barzilai and B. K. Rosen. Comparison of ac self- Testing procedures. In Proc. of International Test Conference, pages 89-94, 1983.
3. S. Bose, P. Agrawal, and V. D. Agrawal. Path delay fault simulation of sequential circuits. IEEE Trans, on VLSI, pages 453-461, December 1993.
4. T. J. Chakraborty, V. D. Agarwal, and M. L. Bushnell. Delay fault models and test generation for random logic sequential circuits. In Proc. of Design Automation Conference, pages 165-172, 1992.
5. S. Devadas and K. Keutzer. Synthesis of robust delay- fault-testable circuits: Practice. IEEE Trans, on Computer-Aided Design, pages 277-300, March 1992.
6. S. Devadas and K. Keutzer. Synthesis of robust delay-fault-testable circuits: Theory. IEEE Trans, on Computer-Aided Design, pages 87-101, January 1992.
7. Bhanu Kapoor. Synthesis and Analysis of Delay Fault Testable Digital Circuits. PhD thesis, Southern Methodist University, Dallas, TX, 1994.
8. C. J. Lin and S. M. Reddy. On delay fault testing in logic circuit. IEEE Trans, on Computer-Aided Design, 6:694-703, September 1987.
9. P. McGreer, A. Saldanha, P. Stephan, R. Bray- Ton, and A. Sangiovanni-Vincentelli. Timing analysis and delay-fault test generation using path recursive functions. In Proc. of International Conference on Computer-Aided Design, pages 180-183, 1991.
10. E. S. Park and M. R. Mercer. Robust and non-robust tests for path delay faults in combinational logic. In Proc. of International Test Conference, pages 10271034, 1987.
11. I. Pomeranz and S. M. Reddy. An efficient non- enumerative method to estimate path delay fault coverage. In Proc. of International Conference on Computer-Aided Design, 1992.
12. Franco P. Preparata and Michael I. Shamos. Computational Geometry: An Introduction. Springer-Verlag, New York, 1985.
13. J. Savir and W. H. McAnney. Random pattern testability of delay faults. IEEE Trans, on Computers, pages 291-300, March 1988.
14. M. H. Schulz, F. Fink, and K. Fuchs. Parallel pattern fault simulation of path delay faults. In Proc. of Design Automation Conference, pages 357-363, 1989.
15. G. L. Smith. A model for delay fault based on paths. In Proc. of International Test Conference, pages 342-349, 1985.
16. T. W. Williams, B. Underwood, and M. R. Mercer. The interdepence between delay optimization of synthesized networks and and testing. In Proc. of Design Automation Conference, pages 87-92, 1991.