Parallel concurrent path-delay fault simulation using single-input change patterns

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 426-431

  Gharaybeh, Marwan A ^a   Bushnell, Michael L ^a   Agrawal, Vishwani D ^a  

^a RUTGERS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; BOOLEAN FUNCTIONS; COMPUTER SIMULATION; ERROR DETECTION; FAILURE ANALYSIS; LOGIC GATES; RANDOM PROCESSES;

MACHINE WORD PARALLELISM; PATH DELAY FAULTS; SINGLE INPUT CHANGE PATTERNS;

INTEGRATED CIRCUIT TESTING;

EID: 0029697596     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)