Built-In Test for Complex Digital Integrated Circuits

IEEE Journal of Solid-State Circuits

Volumn 15, Issue 3, 1980, Pages 315-319

  Könemann, Bernd ^a   Zwiehoff, Günther ^a   Mucha, Joachim ^b  

^a RWTH AACHEN UNIVERSITY   (Germany)

^b LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, DIGITAL;

EID: 0019027134     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1980.1051391     Document Type: Article

References (11)

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9. P. Agrawal and V. D. Agrawal “Probabalistic analysis of random test generation methods for irredundant combinational logic networks,” IEEE Trans. Comput., vol. C-24, pp. 691–695, July 1975.
10. T. W. Williams and E. B. Eichelberger, “Random patterns within a structured sequential logic design,” in Proc. 1977 Semiconductor Test Symp., Cherry Hill, NJ, Oct. 25–27, 1977, pp. 19–27.
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