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Volumn C-35, Issue 4, 1986, Pages 317-321

ACCUMULATOR COMPRESSION TESTING.

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS, VLSI - TESTING;

EID: 0022700735     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1986.1676764     Document Type: Article
Times cited : (27)

References (18)
  • 1
    • 84937076602 scopus 로고
    • A note on testing logic circuits by transition counting
    • S. M. Reddy A note on testing logic circuits by transition counting IEEE Trans. Comput. C-26 313 314 Mar. 1977
    • (1977) IEEE Trans. Comput. , vol.C-26 , pp. 313-314
    • Reddy, S.M.1
  • 2
    • 0017924887 scopus 로고
    • Generation of optimal transition count tests
    • J. P. Hayes Generation of optimal transition count tests IEEE Trans. Comput. C-27 36 41 Jan. 1978
    • (1978) IEEE Trans. Comput. , vol.C-27 , pp. 36-41
    • Hayes, J.P.1
  • 3
    • 0018057724 scopus 로고
    • Testing logic circuits with compressed data
    • H. Fujiwara K. Kinoshita Testing logic circuits with compressed data Proc. FTCS-8 108 113 Proc. FTCS-8 1978
    • (1978) , pp. 108-113
    • Fujiwara, H.1    Kinoshita, K.2
  • 4
    • 0019029565 scopus 로고
    • Syndrome testable design of combinational circuits
    • J. Savir Syndrome testable design of combinational circuits IEEE Trans. Comput. C-29 442 550 June 1980
    • (1980) IEEE Trans. Comput. , vol.C-29 , pp. 442-550
    • Savir, J.1
  • 5
    • 0020588211 scopus 로고
    • Increased effectiveness of built-in-testing by output data modification
    • V. K. Agarwal Increased effectiveness of built-in-testing by output data modification Proc. FTCS-13 227 234 Proc. FTCS-13 1983-June
    • (1983) , pp. 227-234
    • Agarwal, V.K.1
  • 6
    • 0021558356 scopus 로고
    • Higher certainty of error coverage by output data modification
    • Y. Zorian V. K. Agarwal Higher certainty of error coverage by output data modification Proc. 1984 Int. Test Conf. 140 147 Proc. 1984 Int. Test Conf. 1984
    • (1984) , pp. 140-147
    • Zorian, Y.1    Agarwal, V.K.2
  • 7
    • 0019677187 scopus 로고
    • Testing by verifying Walsh coefficients
    • A. K. Susskind Testing by verifying Walsh coefficients Proc. FTCS-11 206 208 Proc. FTCS-11 1981
    • (1981) , pp. 206-208
    • Susskind, A.K.1
  • 8
    • 0021510538 scopus 로고
    • An analysis of the use of Rademacher–Walsh spectrum in compact testing
    • T. C. Hsiao S. Seth An analysis of the use of Rademacher–Walsh spectrum in compact testing IEEE Trans. Comput. C-33 934 937 Oct. 1984
    • (1984) IEEE Trans. Comput. , vol.C-33 , pp. 934-937
    • Hsiao, T.C.1    Seth, S.2
  • 9
    • 0021473881 scopus 로고
    • Spectral fault signatures for single stuck‑at faults in combinational networks
    • D. M. Miller J. C. Muzio Spectral fault signatures for single stuck‑at faults in combinational networks IEEE Trans. Comput. C-33 765 769 Aug. 1984
    • (1984) IEEE Trans. Comput. , vol.C-33 , pp. 765-769
    • Miller, D.M.1    Muzio, J.C.2
  • 11
    • 0004100864 scopus 로고
    • Encyclopedia of Mathematics and its Applications
    • The theory of partitions Addison-Wesley MA, Reading
    • G. E. Andrews Encyclopedia of Mathematics and its Applications 2 1976 Addison-Wesley MA, Reading The theory of partitions
    • (1976) , vol.2
    • Andrews, G.E.1
  • 12
    • 85142956730 scopus 로고
    • D. E. Knuth private communication Nov. 1984
    • (1984)
    • Knuth, D.E.1
  • 13
    • 0016507959 scopus 로고
    • An advanced fault issolation system for digital logic
    • N. Benowitz An advanced fault issolation system for digital logic IEEE Trans. Comput. C-24 489 497 May 1975
    • (1975) IEEE Trans. Comput. , vol.C-24 , pp. 489-497
    • Benowitz, N.1
  • 14
    • 0019029545 scopus 로고
    • Measures of effectiveness of fault signature analysis
    • J. E. Smith Measures of effectiveness of fault signature analysis IEEE Trans. Comput. C-29 510 514 June 1980
    • (1980) IEEE Trans. Comput. , vol.C-29 , pp. 510-514
    • Smith, J.E.1
  • 15
    • 84911268463 scopus 로고
    • The theory of signature testing for VLSI
    • J. L. Carter The theory of signature testing for VLSI Proc. 14th ACM Symp. Theory Comput. 289 296 Proc. 14th ACM Symp. Theory Comput. 1982
    • (1982) , pp. 289-296
    • Carter, J.L.1
  • 16
    • 0021156373 scopus 로고
    • Increased fault coverage through multiple signatures
    • S. Z. Hassan E. J. McCluskey Increased fault coverage through multiple signatures Proc. FTCS-14 354 359 Proc. FTCS-14 1984-June
    • (1984) , pp. 354-359
    • Hassan, S.Z.1    McCluskey, E.J.2
  • 17
    • 0021571225 scopus 로고
    • Can we eliminate fault escape in self testing by polynomial division (signature analysis)
    • D. K. Bhavsar B. Krishnamurthy Can we eliminate fault escape in self testing by polynomial division (signature analysis) Proc. Int. Test Conf. 134 139 Proc. Int. Test Conf. 1984-Oct.
    • (1984) , pp. 134-139
    • Bhavsar, D.K.1    Krishnamurthy, B.2
  • 18
    • 0016961340 scopus 로고
    • Transition count testing of combinational logic circuits
    • J. P. Hayes Transition count testing of combinational logic circuits IEEE Trans. Comput. C-25 613 620 June 1976
    • (1976) IEEE Trans. Comput. , vol.C-25 , pp. 613-620
    • Hayes, J.P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.