Measures of the Effectiveness of Fault Signature Analysis

IEEE Transactions on Computers

Volumn C-29, Issue 6, 1980, Pages 510-514

  Smith, James E ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

Data compression; dependent errors; fault detection; fault signature; linear feedback shift registers

Indexed keywords

COMPUTERS, DIGITAL;

EID: 0019029545     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1980.1675610     Document Type: Article

References (10)

1. R. A. Frohwerk, “Signature analysis: A new digital field service method,” Hewlett-Packard J., pp. 2–8, May 1977.
2. N. Benowitz et al., “An advanced fault isolation system for digital logic,” IEEE Trans. Comput., vol. C-24, pp. 489–497, May 1975.
3. J. P. Hayes, “Transition count testing of combinational logic circuits,” IEEE Trans. Comput., vol. C-25, 613–620, June 1976.
4. H. Fujiwara and K. Kinoshita, “Testing logic circuits with compressed data,” in Proc. 8th Annu. Int. Conf. on Fault-Tolerant Comput., June 1978, pp. 108–113.
5. R. David, “Feedback shift register testing,” in Proc. 8th Ann. Int. Conf. on Fault-Tolerant Comput., June 1978, pp. 103–107.
6. D. A. Anderson, “Design of self-checking digital networks,” Coordinated Sci. Lab. Rep. R-527, University of Illinois, Urbana, Sept. 1971.
7. Hewlett-Packard Corp., A Designers Guide to Signature Analysis, Appl. 222, 1978.
8. W. W. Peterson and E. J. Weldon, Jr., Error-Correcting Codes. Cambridge, MA: MIT Press, 1972.
9. A. Avizienis, “A study of the effectiveness of fault-detecting codes for binary arithmetic,” Jet Propulsion Lab. Tech. Rep. 32–711, Pasadena, CA, Sept. 1965.
10. J. E. Meggitt, “Error correcting codes and their implementation for data transmission systems,” IRE Trans. Inform. Theory, vol. IT-7, pp. 234–244, Oct. 1961.