Arithmetic built-in self test for digital signal processing architectures

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1995, Pages 659-662

  Adham, S ^a   Kassab, M ^a   Mukherjee, N ^a   Radecka, K ^a   Rajski, J ^a   Tyszer, J ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; CONSUMER ELECTRONICS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK ANALYSIS; FAILURE ANALYSIS; VECTORS;

ARITHMETIC BUILT IN SELF TEST; DIGITAL SIGNAL PROCESSING ARCHITECTURES;

INTEGRATED CIRCUIT TESTING;

EID: 0029216768     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)