Accumulator-Based Compaction of Test Responses

IEEE Transactions on Computers

Volumn 42, Issue 6, 1993, Pages 643-650

  Rajski, Janusz ^a   Tyszer, Jerzy ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

Accumulators; built in self test; data path architecture; fault coverage drop; l s complement adders; Markov chains; test response compaction

Indexed keywords

BINARY SEQUENCES; COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS; PARALLEL PROCESSING SYSTEMS; PROGRAMMING THEORY;

ACCUMULATORS; MARKOV CHAIN MODELS; PARALLEL COMPACTION; TEST RESPONSE COMPACTION;

ADDERS;

EID: 0027606683     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.277285     Document Type: Article

References (19)

1. P. H. Bardell, W. H. McAnney, and J. Savir, Built In Test for VLSI: Pseudorandom Techniques. New York: Wiley-Interscience, 1987.
2. R. A. Frohwerk, “Signature analysis: a new digital field services method,” Hewlett-Packard J., pp. 2–8, May 1977.
3. M. Serra, T. Slater, J. C. Muzio, and D. M. Miller, “The analysis of onedimensional linear cellular automata and their aliasing properties,” IEEE Trans. Comput.Aided Design, vol. 9, no. 7, pp. 767–778, July 1990.
4. J. Savir, “Syndrome-testable design of combinational circuits,” IEEE Trans. Comput., vol. C-29, no. 6, pp. 442–451, June 1980.
5. N. R. Saxena and J. P. Robinson, “Accumulator compression testing,” IEEE Trans. Comput., vol. C-35, no. 4, pp. 317–321, Apr. 1986.
6. J. P. Hayes, “Check sum test methods,” Proc. FTCS-6, pp. 114—120, 1976.
7. N. R. Saxena and E. J. McCluskey, “Extended precision checksums,” in Proc. FTCS-I7, pp. 142–147, 1987.
8. M. Damiani, P. Olivio, M. Favalli, and B. Ricco, “An analytical model for the aliasing probability in signature analysis testing,” IEEE Trans. Comput.Aided Design, vol. 8, no. 11, pp. 1133–1144, Nov. 1989.
9. M. Damiani, P. Olivio, M. Favalli, S. Ercolani, and B. Ricco, “Aliasing in signature analysis testing with multiple input shift registers,” IEEE Trans. Comput.Aided Design, vol. 9, no. 12, pp. 1344–1353, Dec. 1990.
10. R. David, “Testing by feedback shift register,” IEEE Trans. Comput., vol. C-29, no. 7, pp. 668–673, July 1980.
11. M. G. Karpovsky, S. K. Gupta, and D. K. Pradhan, “Aliasing and diagnosis probability in MISR and STUMPS using a general error model,” in Proc. Int. Test Conf, pp. 828–839, Oct. 1991.
12. J. E. Smith, “Measures of the effectiveness of fault signature analysis,” IEEE Trans. Comput., vol. C-29, no. 6, pp. 510–514, June 1980.
13. T. W. Williams, W. Daehn, M. Gruetzner, and C. W. Starke, “Bounds and analysis of aliasing errors in linear-feedback shift-registers,” IEEE Trans. Comput.Aided Design, vol. 7, no. 1, pp. 75–83, Jan. 1988.
14. J. Rajski and J. Tyszer, “Experimental analysis of fault coverage in systems with signature registers,” in Proc. 2nd European Test Conf. (Munich, Germany), pp. 45–51, Apr. 1991.
15. B. Koenemann, J. Mucha, and G. Zwiehoff, “Built-in logic block observation techniques,” in Proc. Int. Test Conf 1979 (Cherry Hill, NJ), pp. 37–41, Oct. 1979.
16. E. Blokken, H. de Keulenaer, F. Catthoor, and H. J. de Man, “A flexible module library for custom DSP applications in a multiprocessor environment,” IEEE J. Solid-State Circuits, vol. 25, no. 3, pp. 720–729, June 1990.
17. R. J. Higgins, Digital Signal Processing in VLSI. Englewood Cliffs, NJ: Prentice-Hall, 1990.
18. U. Dudley, Elementary Number Theory. San Francisco: Freeman, 1969.
19. P. Billingsley, Probability and Measure. New York: Wiley, 1986.