메뉴 건너뛰기




Volumn 9, Issue 12, 1990, Pages 1344-1353

Aliasing in Signature Analysis Testing with Multiple Input Shift Registers

Author keywords

Built in self test (BIST); design for testability; linear finite state machines; Markov processes; signature analysis

Indexed keywords

INTEGRATED CIRCUIT TESTING--COMPUTER AIDED ANALYSIS; INTEGRATED CIRCUITS, DIGITAL--TESTING;

EID: 0025590418     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.62779     Document Type: Article
Times cited : (27)

References (22)
  • 1
    • 0002553777 scopus 로고
    • Signature analysis: A new digital field services method
    • May
    • R. A. Frohwerk, “Signature analysis: A new digital field services method,” Hewlett-Packard J., pp. 2–8, May 1977.
    • (1977) Hewlett-Packard J. , pp. 2-8
    • Frohwerk, R.A.1
  • 2
    • 0019027134 scopus 로고
    • Built-in test for complex digital integrated circuits
    • B. Koenemann, J. Mucha, and G. Ziehoff, “Built-in test for complex digital integrated circuits,” IEEE J. Solid-State Circuits, vol. SC-15. pp. 315–319, 1980.
    • (1980) IEEE J. Solid-State Circuits , vol.SC-15 , pp. 315-319
    • Koenemann, B.1    Mucha, J.2    Ziehoff, G.3
  • 3
    • 0021521542 scopus 로고
    • LOCST, A built-in self-test technique
    • Nov.
    • J. J. LeBlanc, “LOCST, A built-in self-test technique,” IEEE Design Test, pp. 45–52, Nov. 1984.
    • (1984) IEEE Design Test , pp. 45-52
    • LeBlanc, J.J.1
  • 4
    • 0023363655 scopus 로고
    • Design and test of the 80386
    • June
    • P. P. Gelsinger, “Design and test of the 80386,” IEEE Design Test, pp. 42–50,June 1876.
    • (1876) IEEE Design Test , pp. 42-50
    • Gelsinger, P.P.1
  • 6
    • 0019029545 scopus 로고
    • Measures of the effectiveness of fault signature analysis
    • J. E. Smith, “Measures of the effectiveness of fault signature analysis,” IEEE Trans. Comput., vol. C-29, pp. 510–514, 1980.
    • (1980) IEEE Trans. Comput. , vol.C-29 , pp. 510-514
    • Smith, J.E.1
  • 7
    • 0016961340 scopus 로고
    • Transition count testing of combinational logic networks
    • J. P. Hayes. “Transition count testing of combinational logic networks,” IEEE Trans. Comput., vol. C-25, pp. 613–620, 1976.
    • (1976) IEEE Trans. Comput. , vol.C-25 , pp. 613-620
    • Hayes, J.P.1
  • 8
    • 0019029565 scopus 로고
    • Syndrome-testable design of combinational circuits
    • J. Savir, “Syndrome-testable design of combinational circuits,” IEEE Trans. Comput., vol. C-33, pp. 442–451, 1980.
    • (1980) IEEE Trans. Comput. , vol.C-33 , pp. 442-451
    • Savir, J.1
  • 9
    • 0020708007 scopus 로고
    • Testing by verifying Walsh coefficients
    • J. Suskind, “Testing by verifying Walsh coefficients,” IEEE Trans. Comput., vol. C-35, pp. 198–201, 1983.
    • (1983) IEEE Trans. Comput. , vol.C-35 , pp. 198-201
    • Suskind, J.1
  • 10
    • 0022700735 scopus 로고
    • Accumulator compression testing
    • N. R. Saxena and J. P. Robinson, “Accumulator compression testing,” IEEE Trans. Comput., vol. C-35, pp. 317–321, 1986.
    • (1986) IEEE Trans. Comput. , vol.C-35 , pp. 317-321
    • Saxena, N.R.1    Robinson, J.P.2
  • 12
    • 0024767782 scopus 로고
    • An analytical model for the aliasing probability in signature analysis testing
    • M. Damiani, P. Olivo, M. Favalli, and B. Ricco, “An analytical model for the aliasing probability in signature analysis testing,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 1133–1145, 1989.
    • (1989) IEEE Trans. Computer-Aided Design , vol.8 , pp. 1133-1145
    • Damiani, M.1    Olivo, P.2    Favalli, M.3    Ricco, B.4
  • 13
    • 0024128167 scopus 로고
    • An iterative technique for calculating aliasing probability of linear feedback signature registers
    • May
    • A. Ivanov and V. K. Agarwal, “An iterative technique for calculating aliasing probability of linear feedback signature registers,” in Proc. FTCS 1988, May 1988, pp. 70–75.
    • (1988) Proc. FTCS 1988 , pp. 70-75
    • Ivanov, A.1    Agarwal, V.K.2
  • 14
    • 0022786257 scopus 로고
    • Signature analysis testing for multioutput circuits
    • R. David, “Signature analysis testing for multioutput circuits,” IEEE Trans. Comput., vol. C-35, pp. 830–837, 1986.
    • (1986) IEEE Trans. Comput. , vol.C-35 , pp. 830-837
    • David, R.1
  • 15
    • 84941860658 scopus 로고
    • Aliasing probability for multiple input signature analyzer and a new compression technique
    • Mar.
    • D. K. Pradhan, S. K. Gupta, and M. G. Karpovsky, “Aliasing probability for multiple input signature analyzer and a new compression technique,” in Proc. IEEE BIST Workshop, Mar. 1989.
    • (1989) Proc. IEEE BIST Workshop
    • Pradhan, D.K.1    Gupta, S.K.2    Karpovsky, M.G.3
  • 16
    • 0038111323 scopus 로고    scopus 로고
    • Analysis and design of linear finite state machines for signature analysis testing
    • to be published.
    • M. Damiani, P. Olivo, and B. Ricco. “Analysis and design of linear finite state machines for signature analysis testing,” IEEE Trans. Comput., to be published.
    • IEEE Trans. Comput.
    • Damiani, M.1    Olivo, P.2    Ricco, B.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.