Test Responses Compaction in Accumulators with Rotate Carry Adders

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 12, Issue 4, 1993, Pages 531-539

  Rajski, Janusz ^a   Tyszer, Jerzy ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT TESTING; RANDOM PROCESSES;

ACCUMULATORS; COMPACTION PROPERTIES; MARKOV CHAINS; ROTATE CARRY ADDERS; TEST RESPONSE COMPACTION;

LOGIC CIRCUITS;

EID: 0027576849     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.229736     Document Type: Article

References (20)

1. P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques. New York: Wiley-Interscience, 1987.
2. E. Blokken, H. de Keulenaer, F. Catthoor, and H. J. de Man, “A flexible module library for custom DSP applications in a multiprocessor environment,” IEEE J. Solid-State Circuits, vol. 25, pp. 720-729, June 1990.
3. P. Billingsley, Probability and Measure. New York: Wiley, 1986.
4. M. Damiani, P. Olivio, M. Favalli, S. Ercolani, and B. Riccò, “Aliasing in signature analysis testing with multiple input shift registers,” IEEE Trans. Computer Aided Design, vol. 9, pp. 1344–1353, Dec. 1990.
5. M. Damiani, P. Olivio, M. Favalli, and B. Riccò, “An analytical model for the aliasing probability in signature analysis testing,” IEEE Trans. Computer Aided Design, vol. 8, pp. 1133–1144, Nov. 1989.
6. R. David, “Testing by feedback shift register,” IEEE Trans. Computers, vol. C-29, pp. 668–673, July 1980.
7. R. A. Frohwerk, “Signature analysis: A new digital field service method,” Hewlett-Packard J., pp. 2–8, May 1977.
8. J. P. Hayes, “Transition count testing of combinational logic circuits,” IEEE Trans. Computers, vol. C-25, pp. 613–620, June 1976.
9. J. P. Hayes, “Check sum test methods,” in Proc. FTCS-6, pp. 114–120, 1976.
10. R. J. Higgins, Digital Signal Processing in VLSI. Englewood Cliffs, NJ: Prentice Hall, 1990.
11. B. Koenemann, J. Mucha, and G. Zwiehoff, “Built-in logic block observation techniques,” in Int. Test Conf. 1979, Cherry Hill, NJ, pp. 37–41, Oct. 1979.
12. J. Rajski and J. Tyszer, “Experimental analysis of fault coverage in systems with signature registers,” in Proc. 2nd European Test Conf., pp. 45–51, Apr. 1991.
13. J. Rajski and J. Tyszer, “Accumulator-based compaction of test responses,” IEEE Trans. Computers, to appear.
14. S. R. Reddy, K. K. Saluja, and M. G. Karpovsky, “A data compression technique for test responses,” IEEE Trans. Computers, vol. C-38, pp. 1151–1156, Sept. 1988.
15. J. Savir, “Syndrome-testable design of combinational circuits,” IEEE Trans. Computers, vol. C-29, pp. 442–451, June 1980.
16. N. R. Saxena and J. P. Robinson, “Accumulator compression testing,” IEEE Trans. Computers, vol. C-35, pp. 317–321, Apr. 1986.
17. N. R. Saxena and E. J. McCluskey, “Extended precision check-sums,” in Proc. ETCS-17, pp. 142–147, 1987.
18. M. Serra, T. Slater, J. C. Muzio, and D. M. Miller, “The analysis of one-dimensional linear cellular automata and their aliasing properties,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 767–778, July 1990.
19. J. E. Smith, “Measures of the effectiveness of fault signature analysis,” IEEE Trans. Computers, vol. C-29, pp. 510–514, June 1980.
20. T. W. Williams, W. Daehn, M. Gruetzner, and C. W. Starke, “Bounds and analysis of aliasing errors in linear-feedback shift-registers,” IEEE Trans. Computer Aided Design, vol. 7, pp. 75–83, Jan. 1988.