Effects of oxide interface traps and transient enhanced diffusion on the process modeling of PMOS devices

IEEE Transactions on Electron Devices

Volumn 43, Issue 7, 1996, Pages 1144-1152

  Vuong, H H ^a   Rafferty, C S ^a   Eshraghi, S A ^a   Lentz, J L ^a   Zeitzoff, P M ^a   Pinto, M R ^a   Hillenius, S J ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DEFECTS; ION IMPLANTATION; OXIDES; SEMICONDUCTING BORON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SILICA;

DEVICE THRESHOLD VOLTAGE; DRAIN INDUCED BARRIER LOWERING EFFECT; OXIDE INTERFACE TRAPPING EFFECT; SHORT CHANNEL EFFECTS; TECHNOLOGY COMPUTER AIDED DESIGN; TRANSIENT ENHANCED DIFFUSION MODEL;

MOS DEVICES;

EID: 0030196624     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.502426     Document Type: Article

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