Measurements and Modeling of the n-Channel MOSFET Inversion Layer Mobility and Device Characteristics in the Temperature Range 60–300 K

IEEE Transactions on Electron Devices

Volumn 37, Issue 5, 1990, Pages 1289-1300

  Huang, Cheng Liang ^a   Gildenblat, Gennady Sh ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR MATERIALS--CHARGE CARRIERS;

INVERSION LAYER MOBILITY; MOBILITY MODEL; MOS TRANSISTOR; N-CHANNEL MOSFET;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0025430936     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.108191     Document Type: Article

References (33)

1. F. H. Gaensslen, V. L. Rideout, E. J. Walker, and J. J. Walker, “Very small MOSFET’s for low-temperature operation,” IEEE Trans. Electron Devices, vol. ED-24, pp. 218–229, 1977.
2. G. Gildenblat, L. Colonna-Romano, D. Lau, and D. E. Nelsen, “Investigation of cryogenic CMOS performance,” in IEDM Tech. Dig., pp. 268–271, 1985.
3. R. M. Fox and R. C. Jaeger, “MOSFET behavior and circuit considerations for analog applications at 77 K,” IEEE Trans. Electron Devices, vol. ED-34, pp. 114–123, 1987.
4. G. Sh. Gildenblat, “Low-temperature CMOS,” in Advanced MOS Device Physics, N. G. Einspruch and G. Sh. Gildenblat Eds. San Diego: Academic Press, 1988.
5. N. D. Arora and G. Sh. Gildenblat, “A semi-empirical model of the MOSFET inversion layer mobility for low-temperature operation,” IEEE Trans. Electron Devices, vol. ED-34, pp. 89–93, 1987.
6. T.-C. Ong, P. K. Ko, and C. Hu, “50-Å gate-oxide MOSFET’s at 77 K,” IEEE Trans. Electron Devices, vol. ED-34, pp. 2129–2135, 1987.
7. S. Takagi, M. Iwase, and A. Toriumi, “On the universality of inversion-layer mobility in N-and P-channel MOSFET’s,” in IEDM Tech. Dig., pp. 398–401, 1988.
8. A. G. Sabnis and J. T. Clemens, “Characterization of the electron mobility in the inverted 〈 100 〉 Si Surface,” in IEDM Tech. Dig., pp. 18–21, 1979.
9. S. C. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1497–1508, 1980.
10. J. T. Watt and J. D. Plummer, “Universal mobility-field curves for electrons and holes in MOS inversion layers,” in Proc. Symp. VLSI Technol. (Tokyo, Japan), pp. 81–82, 1987.
11. T. Ando, A. B. Fowler, and F. Stern, “Electronic properties of two-dimensional systems,” Rev. Mod. Phys., vol. 54, pp. 437–672, 1982.
12. H.-S. Wong, M. H. White, T. J. Krutsick, and R. V. Booth, “Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET’s,” Solid-State Electron., vol. 30, pp. 953–968, 1987.
13. E. H. Nicollian and J. R. Brews, MOS Physics and Technology. New York: Wiley, 1982, ch. 9.
14. D. P. Foty and S. L. Titcomb, “Thermal effects in n-channel enhancement MOSFET’s operated at cryogenic temperatures,” IEEE Trans. Electron Devices, vol. ED-34, pp. 107–113, 1987.
15. C. G. Sodini, T. W. Ekstedt, and J. L. Moll, “Charge accumulation and mobility in thin dielectric MOS transistors,” Solid-State Electron., vol. 25, pp. 833–841, 1982.
16. M. S. Liang, J. Y. Choi, P. K. Ko, and C. Hu, “Inversion-layer capacitance and mobility of very thin gate-oxide MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-33, pp. 409–413, 1986.
17. J. Koomen, “Investigation of the MOST channel conductance in weak inversion,” Solid-State Electron., vol. 16, pp. 801–810, 1973.
18. R. C. Jaeger and F. H. Gaensslen, “Simulation of impurity freezeout through numerical solution of Poisson’s equation with application to MOS device behavior,” IEEE Trans. Electron Devices, vol. ED-27, pp. 914–920, 1980.
19. R. C. Jaeger, F. H. Gaensslen and S. E. Diehl, “An efficient numerical algorithm for simulation of MOS capacitance,” IEEE Trans. Computer-Aided Des., vol. CAD-2, pp. 111–116, 1983.
20. C.-L. Huang and G. Sh. Gildenblat, “MOS flat-band capacitance method at low temperatures,” IEEE Trans. Electron Devices, vol. 36, pp. 1434–1439, 1989.
21. P.-M. D. Chow and K.-L. Wang, “A new ac technique for accurate determination of channel charge and mobility in very thin gate MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1299–1304, 1986.
22. M. Kuhn, “A quasi-static technique for MOS C-V and surface state measurements,” Solid-State Electron., vol. 13, pp. 873–885, 1970.
23. R. Castagne and A. Vapaille, “Description of the SiO2-Si interface properties by means of very low frequency MOS capacitance measurements,” Surface Sci., vol. 28, pp. 157–193, 1971.
24. F. Stern, “Calculated temperature dependence of mobility in silicon inversion layers,” Phys. Rev. Lett., vol. 44, pp. 1469–1472, 1980.
25. D. K. Ferry, “Effects of surface roughness in inversion layer transport,” in 1EDM Tech. Dig., pp. 605–608, 1984.
26. S. Kawaji, “The two-dimensional lattice scattering mobility in a semiconductor inversion layer,” J. Phys. Soc. Japan, vol. 27, pp. 906–908, 1969.
27. S. A. Schwarz and S. E. Russek, “Semi-empirical equations for electron velocity in silicon: Part II—MOS inversion layer,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1634–1639, 1983.
28. M.-S. Lin, “The classical versus the quantum mechanical model of mobility degradation due to the gate field in MOSFET inversion layers,” IEEE Trans. Electron Devices, vol. ED-32, pp. 700–710, 1985.
29. M.-S. Lin, “A better understanding of the channel mobility of Si MOSFET’s based on the physics of quantized subbands,” IEEE Trans. Electron Devices, vol. 35, pp. 2406–2411, 1988.
30. D. S. Jeon and D. E. Burk, “MOSFET electron inversion layer mobilities—A physically based semi-empirical model for a wide temperature range,” IEEE Trans. Electron Devices, vol. 36, pp. 1456–1463, 1989.
31. N. D. Arora and L. M. Richardson, “MOSFET modeling for circuit simulation,” in Advanced MOS Device Physics, N. G. Einspruch and G. Sh. Gildenblat Eds. San Diego: Academic Press, 1988.
32. H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors,” Solid-State Electron., vol. 9, pp. 927–937, 1966.
33. A. Hairapetian, D. Gitlin, and C. R. Viswanathan, “Low-temperature mobility measurements on CMOS devices,” IEEE Trans. Electron Devices, vol. 36, pp. 1448–1455, 1989.