The evolution of the MINIMOS mobility model

Solid State Electronics

Volumn 33, Issue 11, 1990, Pages 1425-1436

  Selberherr, Siegfried ^a   Hänsch, Wilfried ^b   Seavey, Marden ^c   Slotboom, Jan ^d  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^b SIEMENS AG   (Germany)

^c HEWLETT PACKARD COMPANY   (United States)

^d PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; SEMICONDUCTOR MATERIALS;

MINIMOS PROGRAM; SOFTWARE PACKAGE MINIMOS;

SEMICONDUCTOR DEVICES, MOS;

EID: 0025521098     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(90)90117-W     Document Type: Article

References (47)

1. MINIMOS—A two-dimensional MOS transistor analyzer
2. Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature
3. Analysis of Breakdown Phenomena in MOSFET's
4. A two-dimensional model of the avalanche effects in MOS transistors
5. Carrier mobilities in silicon empirically related to doping and field
6. Short-channel MOS transistors in the avalanche-multiplication regime
7. MINIMOS 3: A MOSFET simulator that includes energy balance
8. Electron and hole mobilities in silicon as a function of concentration and temperature
9. Carrier transport near the Si/SiO2 interface of a MOSFET
10. Velocity-field profile of n-silicon: A theoretical analysis
11. MOS device modeling at 77 K
12. Substrate current at cryogenic temperatures: Measurements and a two-dimensional model for CMOS technology
13. Carrier mobilities in silicon semi-empirically related to temperature, doping and injection level
14. The Mobility Model in MINIMOS
15. Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces
16. A long-channel MOSFET model
17. On the universality of inversion-layer mobility in n- and p-channel MOSFETs
18. A semi-empirical model of the MOSFET inversion layer mobility for low-temperature operation
19. A physically based mobility model for MOSFET numerical simulation
20. Transconductance degradation in thin-Oxide MOSFET's
21. Optimum crystallographic orientation of submicrometer CMOS devices operated at low temperatures
22. Proc. VLSI Symposium
23. Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's
24. Device-grade ultra-shallow junctions fabricated with antimony